The IBM High-Level Synthesis System

Camposano, Raúl; Bergamaschi, Reinaldo A.; Haynes, Colin; Payer, Michael; Wu, S. M.

doi:10.1007/978-1-4615-3966-7_4

Cited by 29 publications

(11 citation statements)

References 10 publications

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“…Second, the PRISM-II execution model successfully addresses the issue of executing loops with dynamic loop counts. Third, the proposed execution model possesses several important advantages over existing models proposed in traditional high-level synthesis architectures [18][19][20] and [21]. Traditional high-level synthesis architectures utilize centralized controllers that, in turn, impose strict sequential execution of instructions, resulting in the failure to exploit potential fine-grain parallelism.…”

Section: Model Of Executionmentioning

confidence: 99%

“…Lanneer and colleagues [19] report the CATHEDRAL high-level synthesis environment for automated synthesis of IC architectures for realtime, digital signal processing. IBM's HIS system [20] translates a behavioral description of a synchronous digital system specified in VHDL into a resulting design consisting of a finite state machine and a datapath, both described in the output language BDL/ CS. The Cyber system [21] aims to compile software programs in C and BDL into ASIC chips, called 'software chips'.…”

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confidence: 99%

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An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs

Ghosh

1997

Journal of Network and Computer Applications

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Section: Model Of Executionmentioning

confidence: 99%

mentioning

confidence: 99%

An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs

Ghosh

1997

Journal of Network and Computer Applications

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“…Examples of such high-level synthesis tools can be found in [21][137] [135]. They include general purpose processor synthesis [22][99], low, medium and high throughput digital signal processing [14] [54][87] [100], telecommunication applications [ 106] [ 114], controllers [ 145] [ 130], etc. High level synthesis has recently become commercially available in some domains, [12] for example gives an overview of design tools and methodologies for DSP systems.…”

Section: Hardware Design For Embedded Systemsmentioning

confidence: 99%

Embedded system design

Camposano

Wilberg²

1996

Des Autom Embed Syst

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In the past decade the main engine of electronic design automation has been the widespread application of ASICs (Application Specific Integrated Circuits). Present technology supports complete systems on a chip, most often used as so-called embedded systems in an increasing number of applications. Embedded systems pose new design challenges which we believe will be the driving forces of design automation in the years to come. These include the design of electronic systems hardware, embedded software and hardware / software codesign. This paper explores the novel technical challenges in embedded system design and presents experiences and results of the work in this area using the CASTLE system. CASTLE supports the design of complex embedded systems and the design of the required tools. It provides a central design representation. Verilog, VHDL and C/C++ frontends. Hardware generation in VHDL and BLIF, a retargetable compiler back-end and several analysis and visualization tools. Two design examples, video compression and a diesel injection control, illustrate the presented concepts

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“…High-level-synthesis systems [1]- [4] automatically convert behavioral algorithmic descriptions of design requirements, e.g., control data flow graphs (CDFGs) [5], into optimized register-transfer level (RTL) descriptions in languages such as VHDL or Verilog. Based on a behavioral description, a highlevel-synthesis system determines an allocation of resources, assignment of operations to resources, and a schedule for operations in an attempt to satisfy the design specifications and minimize some combination of delay, area, and power consumption [6]- [17].…”

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confidence: 99%

Unified Incremental Physical-Level and High-Level Synthesis

Wang

Dick

et al. 2007

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Achieving design closure is one of the biggest challenges for modern very large-scale integration system designers. This problem is exacerbated by the lack of high-level designautomation tools that consider the increasingly important impact of physical features, such as interconnect, on integrated circuit area, performance, and power consumption. Using physical information to guide decisions in the behavioral-level stage of system design is essential to solve this problem. In this paper, we present an incremental floorplanning high-level-synthesis system. This system integrates high-level and physical-design algorithms to concurrently improve a design's schedule, resource binding, and floorplan, thereby allowing the incremental exploration of the combined behavioral-level and physical-level design space. Compared with previous approaches that repeatedly call loosely coupled floorplanners for physical estimation, this approach has the benefits of efficiency, stability, and better quality of results. The average CPU time speedup resulting from unifying incremental physical-level and high-level synthesis is 24.72× and area improvement is 13.76%. The low power consumption of a state-of-the-art low-power interconnect-aware high-levelsynthesis algorithm is maintained. The benefits of concurrent behavioral-level and physical-design optimization increased for larger problem instances.Index Terms-Behavioral synthesis, floorplanning, low power design.

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The IBM High-Level Synthesis System

Cited by 29 publications

References 10 publications

An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs

An asynchronous approach to efficient execution of programs on adaptive architectures utilizing FPGAs

Embedded system design

Unified Incremental Physical-Level and High-Level Synthesis

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