Embedded system design

Camposano, Raúl; Wilberg, Jörg

doi:10.1007/bf00134682

Cited by 64 publications

(30 citation statements)

References 80 publications

(70 reference statements)

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“…Such systems also require design flexibility, which results in the need for implementation on programmable processor platform. In fact, embedded software running on RISC and digital signal processing (DSP) processor cores has emerged as a leading implementation methodology for such applications as speech coding, modem functionality, video compression, and communication protocol processing [3], [46]. Current semiconductor technology allows the integration of programmable processors and memory structures on a single die, which enables the implementation of a system on a single chip.…”

Section: A Motivationmentioning

confidence: 99%

“…The goal of the research presented in this paper is to develop the design methodology for the low-power, core-based, realtime SOC based on dynamically variable voltage hardware. We consider real-time systems since almost all embedded systems have to meet real-time constraints dictated by their environment [3]. The key challenge is to develop effective scheduling techniques that treat voltage as a variable to be determined, in addition to the conventional task scheduling and allocation.…”

Section: A Motivationmentioning

confidence: 99%

“…Based on objective functions computed, task T [4] is selected as the most constrained. Once this task is scheduled, the arrival times and deadlines of tasks T [2] and T [3] are updated as shown (see arrows in Fig. 3).…”

Section: B Task Schedulingmentioning

confidence: 99%

“…However, task T [1] can be scheduled at both TR [1,2,3] and TR [5,6,7]. There are five possible schedules with respect to the existing time regions at TR [1,2,3] and three (actually five, but only three distinct) at TR [5,6,7], as shown in the bottom part of Fig. 3.…”

Section: B Task Schedulingmentioning

confidence: 99%

See 3 more Smart Citations

Power optimization of variable voltage core-based systems

Hong¹,

Kirovski

et al. 1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

193

142

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Abstract-The growing class of portable systems, such as personal computing and communication devices, has resulted in a new set of system design requirements, mainly characterized by dominant importance of power minimization and design reuse. The energy efficiency of systems-on-a-chip (SOC) could be much improved if one were to vary the supply voltage dynamically at run time. We develop the design methodology for the lowpower core-based real-time SOC based on dynamically variable voltage hardware. The key challenge is to develop effective scheduling techniques that treat voltage as a variable to be determined, in addition to the conventional task scheduling and allocation. Our synthesis technique also addresses the selection of the processor core and the determination of the instruction and data cache size and configuration so as to fully exploit dynamically variable voltage hardware, which results in significantly lower power consumption for a set of target applications than existing techniques. The highlight of the proposed approach is the nonpreemptive scheduling heuristic, which results in solutions very close to optimal ones for many test cases. The effectiveness of the approach is demonstrated on a variety of modern industrialstrength multimedia and communication applications. Index Terms-High-level synthesis, scheduling, synthesis for low power, system-on-a-chip (SOC).

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Section: A Motivationmentioning

confidence: 99%

Section: A Motivationmentioning

confidence: 99%

Section: B Task Schedulingmentioning

confidence: 99%

Section: B Task Schedulingmentioning

confidence: 99%

See 2 more Smart Citations

Power optimization of variable voltage core-based systems

Hong¹,

Kirovski

et al. 1998

Proceedings of the 35th Annual Conference on Design Automation Conference - DAC '98

193

142

View full text Add to dashboard Cite

show abstract

“…Such systems also require high design flexibility, which results in the need for implementation on programmable processor platforms. In fact, embedded software running on RISC or digital signal processor (DSP) cores has emerged as a leading implementation methodology for such applications as speech coding, modem functionality, video compression, and communication protocol processing [6].…”

Section: Introductionmentioning

confidence: 99%

Task Scheduling for Power Optimisation of Multi Frequency Synchronous Data Flow Graphs

Knerr¹,

Holzer²,

Rupp³

2005

2005 18th Symposium on Integrated Circuits and Systems Design

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During recent years power optimisation has become one of the most challenging design goals in modern communication systems, particularly in the wireless domain. Many different approaches for task scheduling on single or multi-core systems exist, mostly addressing the minimisation of execution time or the number of processors used. The minimisation of the processor's clock frequency by adjusting the supply voltage or directly by frequency scaling according to the chosen task scheduling has shown good results in the reduction of power consumption. Most of the known approaches base their core algorithms on graph representations for multirate systems or synchronous data flow (SDF) graphs, in a single frequency domain. In many cases a signal processing system comprises several frequency domains, in which processes have to be fired according to their in-and output data rates as well as to their frequency domain. In this work the superposition of frequency domains and data dependencies is incorporated into the optimisation process and used as a another degree of freedom. Several algorithms have been implemented and evaluated to minimise the required processor's clock frequency, including a greedy, a simulated annealing, as well as a tabu search approach.

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