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In the context of synthesis, scheduling assigns operations to control steps. Operations are the atomic components used for describing behavior, for example, arithmetic and Boolean operations. They are ordered partially by data dependencies (data-flow graph) and by control constructs such as conditional branches and loops (controlflow graph). A control step usually corresponds to one state, one clock cycle, or one microprogram step. This paper presents a new, pathbased scheduling algorithm. It yields solutions with the minimum number of control steps, taking into account arbitrary constraints that limit the amount of operations in each control step. The result is a finite state machine that implements the control. Although the complexity of the algorithm is proportional to the number of paths in the control-flow graph, it is shown to be practical for large examples with thousands of nodes.

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The automation of the design of electronic systems and circuits [electronic design automation (EDA)] has a history of strong innovation. The EDA business has profoundly influenced the integrated circuit (IC) business and vice-versa. This paper reviews the technologies, algorithms, and methodologies that have been used in EDA tools and the business impact of these technologies. In particular, we will focus on four areas that have been key in defining the design methodologies over time: physical design, simulation/verification, synthesis, and test. We then look briefly into the future. Design will evolve toward more software programmability or some other kind of field configurability like field programmable gate arrays (FPGAs). We discuss the kinds of tool sets needed to support design in this environment.

In the past decade the main engine of electronic design automation has been the widespread application of ASICs (Application Specific Integrated Circuits). Present technology supports complete systems on a chip, most often used as so-called embedded systems in an increasing number of applications. Embedded systems pose new design challenges which we believe will be the driving forces of design automation in the years to come. These include the design of electronic systems hardware, embedded software and hardware / software codesign. This paper explores the novel technical challenges in embedded system design and presents experiences and results of the work in this area using the CASTLE system. CASTLE supports the design of complex embedded systems and the design of the required tools. It provides a central design representation. Verilog, VHDL and C/C++ frontends. Hardware generation in VHDL and BLIF, a retargetable compiler back-end and several analysis and visualization tools. Two design examples, video compression and a diesel injection control, illustrate the presented concepts

Programmable circuit design has played an important role in improving design productivity over the last few decades. By imposing structure on the design, efficient automation of synthesis, placement and routing is possible. We focus on a class of programmable circuits known as mask programmable circuits. In this paper, we describe key issues in design and tool methodology that need to be addressed in creating a programmable fabric. We construct an efficient design flow that can explore different logic and routing architectures. The main advantage of our work is that we tailor tools designed for standard cell design, that are readily available in the market, to work on a programmable fabric. Our flow requires some additional software capability. A special router that understands programmable routing constructs to complete connections is described. In addition, a tool that packs logic efficiently after synthesis is also presented.

In this tutorial, the author describes how high-level synthesis bridges the gap between behavioral specifications and hardware structure by automatically generating a circuit description from a netlist. The resulting description can be used for other design automation tools such as logic synthesis and layout. Describing high-level synthesis for synchronous digital hardware, the author explains the steps of the process, which include compilation, transformation, scheduling, and allocation.igh-level synthesis bridges the gap between the high-level behavioral specification of a digital circuit and its structure. As opposed to logic synthesis, which optimizes only combina-H tional logic, high-level synthesis deals with memory elements, the interconnection structure, such a s buses and multiplexers, and the sequential aspects of a design. The behavioral specification aims at describing only the functionality of a circuit, or what the circuit must do. The specification is usually in a sequential or procedural language similar to programming languages such a s C or Pascal-for example, sequential VHDL. Circuit structure, on the other hand, gives strong hints about the circuit's implementation, or how it is built. The structure is described by a netlist, a list of components and their interconnections.The first step in synthesis is to compile a specification into an internal representation. The second step is to apply high-level transformations with the goal of optimizing the behavior. Finally, scheduling and allocation convert the behavior into a structure. Scheduling determines the time at which each operation is executed, while allocation synthesizes the necessary hardware to perform the operations. The structure is then passed to other design tools for logic synthesis. The advantage of high-level synthesis is that behavioral specifications are generally shorter than lower level structural specifications. Thus, they are easier to write, understand, and change. This makes them less error prone and faster to simulate, which makes the design of complex systems easier and allows a considerably shorter design cycle. But, a s is often the case, automation at this level also exacts a price, and we may have to trade advantages for larger or slower hardware. Moreover, design automation cannot generally match the abilities of a skilled human designer. Despite these drawbacks, design automation does increase productivity significantly. ~ DESIGN REPRESENTATIONA requisite for high-level synthesis is the precise definition of circuit behavior and structure and the systematic classification of design representations. As Table 1 shows, this definition and classification commonly involves two orthogonal axes: the domain and the level. There are three domains: the behavioral, the structural, and the physical. Ideally, pure behavior is described in terms of a n input-output relationship, such as a set of Boolean equations for a combinational network. The structure describes the topology of a system and is typically given 0740-7475/90/001...

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