The high-level synthesis of digital systems

McFarland, Michael C.; Parker, Alice C.; Camposano, Raúl

doi:10.1109/5.52214

Cited by 497 publications

(130 citation statements)

References 63 publications

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“…Depending on the design space exploration approach, the DP optimization techniques are partitioned into global and local (Mcfarland, 1990). Both of them can fold the DP graph by merging variables, operators, and data dependences.…”

Section: Compatibility Of Variablesmentioning

confidence: 99%

Methods and tools for high and system level synthesis

Prihozhy

1997

VLSI: Integrated Systems on Silicon

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This paper presents new methods for high-and system-level synthesis based on transformation of a behavioral description to a special behavioral model, development of new and modification of existing synthesis techniques for this model, development of net-based synthesis model and techniques extending target architectures. VHDL-based high-level synthesis tools running on an IBM PC platform are described.

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Section: Compatibility Of Variablesmentioning

confidence: 99%

Methods and tools for high and system level synthesis

Prihozhy

1997

VLSI: Integrated Systems on Silicon

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“…Initially confined to data path designs, HLS tools are now commenced to address complete systems, including control logic, complex on-chip and off-chip interconnections. HLS [9] tools provide design modeling, synthesis, and validation at a higher level of abstraction. This makes computation cheaper, smaller, and less power hungry, thus enabling more sophisticated system design for complex HPC applications.…”

Section: Introductionmentioning

confidence: 99%

AMC: Advanced Multi-accelerator Controller

Hussain

Haider²,

Gursal³

et al. 2015

Parallel Computing

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The rapid advancement, use of diverse architectural features and introduction of High Level Synthesis (HLS) tools in FPGA technology have enhanced the capacity of data-level parallelism on a chip. A generic FPGA based HLS multiaccelerator system requires a microprocessor (master core) that manages memory and schedules accelerators. In a real environment, such HLS multi-accelerator systems do not give a perfect performance due to memory bandwidth issues. Thus, a system demands a memory manager and a scheduler that improves performance by managing and scheduling the multi-accelerator's memory access patterns efficiently. In this article, we propose the integration of an intelligent memory system and efficient scheduler in the HLS-based multi-accelerator environment called Advanced Multi-accelerator Controller (AMC). The AMC system is evaluated with memory intensive accelerators, High Performance Computing (HPC) applications and implemented and tested on a Xilinx Virtex-5 ML505 evaluation FPGA board. The performance of the system is compared against the microprocessorbased systems that have been integrated with the operating system. Results show that the AMC based HLS multi-accelerator system achieves 10.4x and 7x of speedup compared to the MicroBlaze and Intel Core based HLS multi-accelerator systems.

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“…Numer ous algorithms have been proposed for scheduling [2], [4]r [5], [7], [8]. An excellent overview of existing scheduling algorithms appears in [6]. An integer linear programming approach to scheduling is described in [7] and [8].…”

Section: Introductionmentioning

confidence: 99%