The Future of Non-planar Nanoelectronics MOSFET Devices: A Review

Riyadi, Munawar Agus; Suseno, Jatmiko Endro; Ismail, Razali

doi:10.3923/jas.2010.2136.2146

Cited by 19 publications

(13 citation statements)

References 57 publications

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“…All the mentioned techniques fall under hydrothermal synthesis and one of the preferred methods is atomic layer deposition (ALD). The ALD process is capable of producing highly conformal and quality films [21]. The process is cyclic and is based on the number of reactants.…”

Section: Growth Techniques Of Znomentioning

confidence: 99%

ZnO Nanowire Field Effect Transistor for Biosensing: A Review

Ditshego

2019

JNanoR

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The last 19 years have seen intense research made on zinc oxide (ZnO) material mainly due to the ability of converting the natural n-type material into p-type. For a long time, the p-type state was impossible to attain and maintain. The review focuses on ways of improving the doped ZnO material which acts as a channel for nanowire field effect transistor (NWFET) and biosensor. The biosensor has specific binding which is called functionalisation achieved by attaching a variety of compounds on the designated sensing area. Reference electrodes and buffers are used as controllers. Top-down fabrication processes are preferred over bottom-up because they pave way for mass production. Different growth techniques are reviewed and discussed. Strengths and weaknesses of the FET and sensor are also reviewed.

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Section: Growth Techniques Of Znomentioning

confidence: 99%

ZnO Nanowire Field Effect Transistor for Biosensing: A Review

Ditshego

2019

JNanoR

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“…3 To sustain historical device scaling and mitigate unfavorable SCEs, nonconventional and nonplanar device architectures have been reported to provide enhanced channel control. 4 Multigate MOSFETs on the concept of volume inversion of charge provides enhanced carrier mobility, better I ON /I OFF ratio, and are widely recognized as one of the promising candidates to meet the predictions of International Technology Roadmap for Semiconductor (ITRS). 5 Trigate MOSFET has been reported to boost the device performance at nanoscale as these devices enable better gate control over the channel and optimal subthreshold characteristics.…”

Section: Introductionmentioning

confidence: 99%

Three‐dimensional analytical modeling and performance analysis of triple material trigate silicon‐on‐insulator MOSFET

Shora

Khanday

2019

Int J Numerical Modelling

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The semiconductor industry has implemented the technique of wrapping the gate electrode on different sides of channel to mitigate the degrading electrostatic effects in nanometer transistor. Intel adopted trigate architecture, wherein the channel is surrounded by gate electrode on three sides to improve the gate control over the channel. In order to further enhance the performance and diminish the short channel effects, triple material trigate silicon-oninsulator (SOI) MOSFET is explored in this work. An analytical model to determine the device electrostatics and match deviations due to device geometry has also been developed. The consequence of quantum confinement effects (QMEs), which arise due to ultra-thin body structure, on the inversion charge and threshold voltage has also been included. Thus, the analytical model presented in this work is based on a self-consistent solution of threedimensional Poisson's equation and two-dimensional Schrodinger equation with proper boundary conditions. The model is verified by the uniformity obtained between the results from analytical model and TCAD simulations. The superiority of the device has been demonstrated by comparing performance parameters like potential distribution, field variations, drain induced barrier lowering (DIBL) with already existing device structures like single material trigate (SMTG) and dual material trigate (DMTG) SOI MOSFETs

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“…Double-gate MOSFET's structure has been proven to be less sensitive to SCE mainly because of its excellent electrostatic control over the channel region [8][9][10][11]. The mobility of the electrons/holes within the conductive channel are improved due to its excellent gate control that allows a significant amount of volume inversion [12]. The current drivability in the double-gate structure can be improved without having any increment in the area by simply etching the silicon body a lot more thinner [13,14].…”

Section: Introductionmentioning

confidence: 99%

Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

2019

IJRTE

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Aggressive scaling of Metal-oxide-semiconductor Field Effect Transistors (MOSFET) have been conducted over the past several decades and now is becoming more intricate due to its scaling limit and short channel effects (SCE). To overcome this adversity, a lot of new transistor structures have been proposed, including multi gate structure, high-k/metal gate stack, strained channel, fully-depleted body and junctionless configuration. This paper describes a comprehensive 2-D simulation design of a proposed transistor that employs all the aforementioned structures, named as Junctionless Strained Double Gate MOSFETs (JLSDGM). Variation in critical design parameter such as gate length (L g ) is considered and its impact on the output properties is comprehensively investigated. The results shows that the variation in gate length (L g ) does contributes a significant impact on the drain current (I D ), on-current (I ON ), off-current (I OFF ), I ON /I OFF ratio, subthreshold swing (SS) and transconductance (g m ). The JLSDGM device with the least investigated gate length (4nm) still provides remarkable device properties in which both I ON and g m (max) are measured at 1680 µA/µm and 2.79 mS/µm respectively. Engineering (FKEKK), UTeM. Her research interest includes process and device simulation of nanoscale MOSFETs device, advanced CMOS design, optimization approach (DOE) and process parameter variability. Z. A. F. M. Napiah received the B.Eng. degree in electrical engineering and the M.Eng. degree in Microelectronic from Universiti Teknologi Malaysia (UTM). He received the Ph.D. degree in Microelectronics from Kanawa University, Japan. He is currently a senior lecturer at Faculty of Electronic and Computer Engineering (FKEKK), UTeM. His research interest includes process and device simulation of MOSFET device, advanced CMOS design and CMOS based Photodetector and Photoreceiver.

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The Future of Non-planar Nanoelectronics MOSFET Devices: A Review

Cited by 19 publications

References 57 publications

ZnO Nanowire Field Effect Transistor for Biosensing: A Review

ZnO Nanowire Field Effect Transistor for Biosensing: A Review

Three‐dimensional analytical modeling and performance analysis of triple material trigate silicon‐on‐insulator MOSFET

Design Consideration and Impact of Gate Length Variation on Junctionless Strained Double Gate MOSFET

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