The Future of Nanometer SOC Design

Leibson, Steve

doi:10.1109/issoc.2006.321999

Cited by 4 publications

(2 citation statements)

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“…In current technologies, a phit 1 size equal to 32 or 64 bits underutilizes the amount of wires that can be implemented to connect neighbor routers. Consider for example a SoC region as depicted in Figure 2, using a 90 nm technology, with 140 nm wire pitch and 0.1 mm 2 router area [16]. Even considering the use of only one metal layer, each router could be connected to its neighbor using up to 2258 wires.…”

Section: Router Channel Multiplexingmentioning

confidence: 99%

A New Router Architecture for High-Performance Intrachip Networks

Carara¹,

Calazans²,

Moraes³

2020

JICS

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For almost a decade now, Network on Chip (NoC) concepts have evolved to provide an interesting alternative to more traditional intrachip communication architectures (e.g. shared busses) for the design of complex Systems on Chip (SoCs). A considerable number of NoC proposals are available, focusing on different sets of optimization aspects, related to specific classes of applications. Each such application employs a NoC as part of its underlying implementation infrastructure. Many of the mentioned optimization aspects target results such as Quality of Service (QoS) achievement and/or power consumption reduction. On the other hand, the use of NoCs brings about the solution of new design problems, such to the choice of synchronization method to employ between NoC routers and application modules mapping. Although the availability of NoC structures is already rather ample, some design choices are at base of many, if not most, NoC proposals. These include the use of wormhole packet switching and virtual channels. This work pledges against this practice. It discusses trade-offs of using circuit or packet switching, arguing in favor the use of the former with fixed size packets (cells). Quantitative data supports the argumentation. Also, the work proposes and justifies replacing the use of virtual channels by replicated channels, based on the abundance of wires in current and expected deep sub-micron technologies. Finally, the work proposes a transmission method coupling the use of session layer structures to circuit switching to better support application implementation. The main reported result is the availability of a router with reduced latency and area, a communication architecture adapted for high-performance applications.

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Section: Router Channel Multiplexingmentioning

confidence: 99%

A New Router Architecture for High-Performance Intrachip Networks

Carara¹,

Calazans²,

Moraes³

2020

JICS

View full text Add to dashboard Cite

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“…Consider for example a 90 nm technology, 140 nm wire pitch and 0.1 mm 2 router area [16]. Each router could be connected to its neighbor through 715 wires (Figure 1), considering the use of only one metal layer.…”

Section: Multiplexing Strategies In Nocsmentioning

confidence: 99%

Router architecture for high-performance NoCs

Carara

Moraes

Calazans

2007

Proceedings of the 20th Annual Conference on Integrated Circuits and Systems Design

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A considerable number of NoC designs are available, focusing on different aspects of this type of communication infrastructure. Example of relevant aspects considered during NoC design are quality-of-service achievement, the choice of synchronization method to employ between routers, power consumption reduction and application modules mapping. However, some design choices are common to many if not most NoC proposals: wormhole packet switching and the use of virtual channels. This work discusses trade-offs on using circuit and packet switching, arguing in favor of the former with fixed packet size. Next, it proposes and justifies the replacement of virtual channels by replicated channels, based on the abundance of wires expected in current and future deep sub-micron technologies. Finally, the work proposes the use of a session layer coupled to circuit switching. Results point out to reduced latency and router area, leading to a router architecture adapted for high-performance NoCs.

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Using a Linear Sectioned Bus And a Communication Processor to Reduce Energy Costs in Synchronous On-Chip Communication

Heyrman

Papanikolaou

Catthoor

et al. 2007

2007 International Symposium on System-on-Chip

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The sectioned bus is an energy-optimal architecture II. ENERGY-OPTIMAL SECTIONED Bus for system-on-chip (SoC) communication, where we save energyThe purpose of the energy-optimal sectioned bus (ESB) by consequently switching off unused bus sections on a cycle-is to allow low-energy operation of intra-tile communication by-cycle basis. The communication processor is a paradigm for the control of such a bus by means of software. Synchronous systems, between memories and the processor, in the deep communication takes place within the tiles of a SoC in the deep sub-micron (DSM) domain. This is done by switching off wire sub-micron technology domain. We explore design alternatives sections that are not used, cycle-by-cycle, to avoid unnecesfor a linear software-controlled sectioned bus while building the sarily charging the capacity associated with the wire. Beside hardware model of a single-instruction-issue processor, and run, consuming little energy, desirable properties for this type of in simulation, a media benchmark on it. We determine the energy cost of controlling this bus, compare it with the energy gain communication are: scalability with the number of ports, with obtained from the sectioning, and find it favorable. The control the number of channels required, and with technology; further cost is only 5% of the bus transport energy, leaving us with a also low latency, little wire congestion, easy floor-planning, gain by segmentation of 81%. We demonstrate the feasibility Of and suitability for optimizing design procedures. the control of a low-power synchronous communication systemWithin a tile we see all events, including memory access by the processor. Starting out from this case study at the lowend to medium range of network complexity, we consider the and ftes,cas go e y a ogramc ahe memories implications of growing complexity that will arise from using are not predictable. They are often considered [14], [20] multiple sectioned buses on multiple-issue computers (VLIWs). unsuitable for low power designs. Memory hierarchies with We find that control of linear bus topologies of medium-level many scratchpads [15] are a useful alternative. Programmed complexity is now well understood. Further work is needed at control serves us well when affronting one implication of the the high-end of non-linear topologies.ESB, which is that we have to drive all sectioning switches with proper control codes for every cycle. The sectioning I. INTRODUCTION process is too complex to be efficiently controlled by the hardware alone. Hardwired control would in any case not On-chip synchronous communication benefits in energy scale well with high bandwidth or complexity. We see this efficiency from sectioning the connection wires with section-as an application of Wilkes' [22] principle on the superiing switches [19] . How these switches should optimally ority of micro-programming over hardware units. Moreover, be controlled has not been studied up to now. Neither has programmed control allows us to adapt communication in a co...

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The Future of Nanometer SOC Design

Cited by 4 publications

References 0 publications

A New Router Architecture for High-Performance Intrachip Networks

A New Router Architecture for High-Performance Intrachip Networks

Router architecture for high-performance NoCs

Using a Linear Sectioned Bus And a Communication Processor to Reduce Energy Costs in Synchronous On-Chip Communication

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