A New Router Architecture for High-Performance Intrachip Networks

Carara, Everton Alceu; Calazans, Ney; Moraes, Fernando

doi:10.29292/jics.v3i1.278

Cited by 15 publications

References 19 publications

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An efficient NoC router design by using an enhanced AES with retiming and clock gating techniques

Venkataraman

Kumar

2019

Trans Emerging Tel Tech

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A system-on-a-chip (SoC) processor core contains several numbers of chips integrated into a single chip where each and every integrated circuit (IC) consists of multiple blocks. Hence, data routing from one chip to another creates a difficult issue in the SoC. A network-on-a-chip (NoC) router has been mainly used to obtain highly reliable data transmission from a source to a destination using low power, low hardware complexity, and high speed to achieve efficient routing in the SoC core, which contains a router, network links (NLs), and network interface (NI). The heart of the NoC core, ie, the router, consists of a finite state machine (FSM), input/output FIFO, a crossbar switch, and an arbiter; however, the XY routing technique was incorporated into the NoC router to achieve high switching speed, and the FSM is used as a controller for the router along with the data stored in FIFO. The multiplexing and demultiplexing operations were also carried out in the crossbar switch in which a grant signal is being generated using the compact round-robin arbiter and an Advanced Encryption Standard (AES) scheme, which is incorporated into the NoC router to achieve high reliability. The chief goal is to establish an efficient NoC router using an improved AES algorithm to achieve high reliability, small chip size, low power consumption, and high performance. Similarly, an optimized composite S-box is designed using a compact multiplicative inverse unit with an improved inverse MixColumns structure proposed using compact 09, 0b, 0d, and 0e operations and retiming pipelined inclusively with clock gating methods (CGMs) applied in the targeted AES scheme. Hence, the retiming method can be used to shrink the number of registers by placing the register in an optimum location with low area and power in retiming-based AES. The switching activity of the clock signal is reduced by using the CGM, which has low power consumption and high speed for clock gating-based AES. Therefore, the high performance-based AES is designed using a pipelined technique with high chip size and power due to the insertion of a large number of registers into the AES circuits. Five types of AES structures are designed, and the die size, delay, power, and 90% security with an optimized AES technique incorporated into a 3×3 NoC router with mesh topology are analyzed. Finally, the comparison between the existing and proposed NoC routers was carried out to analyze the area, delay, and power (ADP) product, and the NoC router design was formulated using Verilog HDL, and limitations along the synthesis process were executed using a ModelSim and Xilinx ISE tools.

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An efficient NoC router design by using an enhanced AES with retiming and clock gating techniques

Venkataraman

Kumar

2019

Trans Emerging Tel Tech

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Design and analysis of application specific network on chip for reliable custom topology

Venkataraman

Kumar

2019

Computer Networks

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A low-latency modular switch for CMP systems

Roca

Flich

Silla

et al. 2011

Microprocessors and Microsystems

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As technology advances, the number of cores in Chip MultiProcessor systems and MultiProcessor Systems-on-Chips keeps increasing. The network must provide sustained throughput and ultra-low latencies.In this paper we propose new pipelined switch designs focused in reducing the switch latency. We identify the switch components that limit the switch frequency: the arbiter. Then, we simplify the arbiter logic by using multiple smaller arbiters, but increasing greatly the switch area. To solve this problem, a second design is presented where the routing traversal and arbitrations tasks are mixed. Results demonstrate a switch latency reduction ranging from 10 to 21%. Network latency is reduced in a range from 11 to 15%.

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A New Router Architecture for High-Performance Intrachip Networks

Cited by 15 publications

References 19 publications

An efficient NoC router design by using an enhanced AES with retiming and clock gating techniques

An efficient NoC router design by using an enhanced AES with retiming and clock gating techniques

Design and analysis of application specific network on chip for reliable custom topology

A low-latency modular switch for CMP systems

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