Design and analysis of application specific network on chip for reliable custom topology

Venkataraman, Natrajan; Kumar, R.

doi:10.1016/j.comnet.2019.03.014

Cited by 21 publications

(16 citation statements)

References 21 publications

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“…Here, the NoC router 21,24 consists of five inputs, such as data in local, data in north, data in west, data in south, and data in south based on the request that any of the data is routed via a destination port at a time and that the remaining four ports stay at zero value. The 5:1 multiplexer has been designed by using four 2:1 MUX and three input selection lines giving only one 8-bit data, and the decoder has been used to convert 8-bit into 128-bit.…”

Section: Existing Noc Router With Regular Aesmentioning

confidence: 99%

An efficient NoC router design by using an enhanced AES with retiming and clock gating techniques

Venkataraman

Kumar

2019

Trans Emerging Tel Tech

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A system-on-a-chip (SoC) processor core contains several numbers of chips integrated into a single chip where each and every integrated circuit (IC) consists of multiple blocks. Hence, data routing from one chip to another creates a difficult issue in the SoC. A network-on-a-chip (NoC) router has been mainly used to obtain highly reliable data transmission from a source to a destination using low power, low hardware complexity, and high speed to achieve efficient routing in the SoC core, which contains a router, network links (NLs), and network interface (NI). The heart of the NoC core, ie, the router, consists of a finite state machine (FSM), input/output FIFO, a crossbar switch, and an arbiter; however, the XY routing technique was incorporated into the NoC router to achieve high switching speed, and the FSM is used as a controller for the router along with the data stored in FIFO. The multiplexing and demultiplexing operations were also carried out in the crossbar switch in which a grant signal is being generated using the compact round-robin arbiter and an Advanced Encryption Standard (AES) scheme, which is incorporated into the NoC router to achieve high reliability. The chief goal is to establish an efficient NoC router using an improved AES algorithm to achieve high reliability, small chip size, low power consumption, and high performance. Similarly, an optimized composite S-box is designed using a compact multiplicative inverse unit with an improved inverse MixColumns structure proposed using compact 09, 0b, 0d, and 0e operations and retiming pipelined inclusively with clock gating methods (CGMs) applied in the targeted AES scheme. Hence, the retiming method can be used to shrink the number of registers by placing the register in an optimum location with low area and power in retiming-based AES. The switching activity of the clock signal is reduced by using the CGM, which has low power consumption and high speed for clock gating-based AES. Therefore, the high performance-based AES is designed using a pipelined technique with high chip size and power due to the insertion of a large number of registers into the AES circuits. Five types of AES structures are designed, and the die size, delay, power, and 90% security with an optimized AES technique incorporated into a 3×3 NoC router with mesh topology are analyzed. Finally, the comparison between the existing and proposed NoC routers was carried out to analyze the area, delay, and power (ADP) product, and the NoC router design was formulated using Verilog HDL, and limitations along the synthesis process were executed using a ModelSim and Xilinx ISE tools.

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Section: Existing Noc Router With Regular Aesmentioning

confidence: 99%

An efficient NoC router design by using an enhanced AES with retiming and clock gating techniques

Venkataraman

Kumar

2019

Trans Emerging Tel Tech

Self Cite

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“…The electric field on the gate insulator and the high-temperature state accelerate aging due to NBTI. This electric field separates the Si-H boundary generated in the process, creating a trap at the interface of the silicon and the gate insulator, and increasing the threshold voltage of the p-type transistor [4,5,11]. This study employs the NBTI model proposed in [23] presented in Equation (10).…”

Section: Aging-induced Delay Modelmentioning

confidence: 99%

“…When the delay prediction is repeated on the 13-bit wire, and the minimum value of p is fixed to 5, the parity bit calculation required for the aging-aware ECC of the link is complete. 4 5 6…”

Section: Non-uniform Ecc Generationmentioning

confidence: 99%

“…In the recent decades, the parallel communication performance of network-on-chip (NoC) has been demonstrated in manycore system-on-chip (SoC) interconnect architectures [1][2][3][4]. Recently, research has been actively conducted on heterogeneous manycore architectures that integrate processing elements (PEs) on a single chip to form a chip multiprocessor (CMP) solution [2,4]. For the multi-level integration of the heterogeneous manycore system, existing NoC architectures such as the ring, mesh, and tree exhibit limitations in terms of providing scalability and low latency.…”

Section: Introductionmentioning

confidence: 99%

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Aging-Resilient Topology Synthesis of Heterogeneous Manycore Network-On-Chip Using Genetic Algorithm with Flexible Number of Routers

2019

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As semiconductor processes enter the nanoscale, system-on-chip (SoC) interconnects suffer from link aging owing to negative bias temperature instability (NBTI), hot carrier injection (HCI), and electromigration. In network-on-chip (NoC) for heterogeneous manycore systems, there is a difference in the aging speed of links depending on the location and utilization of resources. In this paper, we propose a heterogeneous manycore NoC topology synthesis that predicts the aging effect of each link and deploys routers and error correction code (ECC) logic. Aging-aware ECC logic is added to each link to achieve the same link lifetime with less area and latency than the Bose-Chaudhuri-Hocquenghem (BCH) logic. Moreover, based on the modified genetic algorithm, we search for a solution that minimizes the average latency while ensuring the link lifetime by changing the number of routers, location, and network connectivity. Simulation results demonstrate that the aging-aware topology synthesis reduces the average latency of the network by up to 26.68% compared with the aging analysis and the addition of ECC logic on the link after the topology synthesis. Furthermore, topology synthesis with aging-aware ECC logic reduces the maximum average latency by up to 39.49% compared with added BCH logic.improve NoC performance in heterogeneous manycore NoC designs. Existing schemes have applied a fixed number of routers in the chip. These methods make it possible to find a reasonable solution in NoC with a specific number of routers. However, in situations where the number of routers is not assigned, algorithms must be executed several times for different numbers of routers, which requires additional computation time.In contrast, due to the miniaturization of semiconductor processes, delay faults in communication data due to the aging of flip-flops and metal wires have become a significant concern in the SoC interconnect design [8][9][10]. In the nanoscale process, aging-induced delay faults occur mainly due to negative bias temperature instability (NBTI), hot carrier injection (HCI), and electromigration [11][12][13][14][15]. NBTI and HCI increase the threshold voltage of the transistors, and electromigration increases the resistance in metal wires, resulting in longer data transfer delay [8,9,15].Few studies have considered the aging effect in the high-level design of the on-chip interconnect, because it was treated as a low-level design problem. However, recent studies show that in the topology synthesis of heterogeneous manycore NoC, the aging process can be predicted based on the length and communication load of each link [14][15][16]. If the aging effect of each link is taken into consideration during the NoC topology synthesis, it is possible to reduce the performance degradation through the placement of interconnect modules and links. Moreover, this will aid in the recovery of aging resilience by correcting the error even if a delay fault occurs by using the error correction logic.The forward error correction, based on error cor...

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“…New classes and families of such optimal structures are constructed on the basis of both regular [ 7 , 8 , 9 ] and irregular [ 10 ] network topologies. The NoC topology itself has a decisive influence on NoC performance [ 11 , 12 ].…”

Section: Introductionmentioning

confidence: 99%

Routing in triple loop circulants: A case of networks-on-chip

Romanov

Starykh

2020

Heliyon

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In this paper we propose and analyze various approaches to organizing routing in a triple loop circulant topologies as applied to networks-on-chip: static routing based on universal graph search algorithms, such as Dijkstra's algorithm and a possible implementation using Table routing; algorithms created analytically based on an engineering approach with taking into account the structural features of triple loop circulant graphs (Advanced clockwise, Direction selection); an algorithm created on the basis of a mathematical analysis of graph structure and solving the problem of enumerating coefficients at generators (Coefficients finding algorithm). Efficiency, maximum graph paths, occupied memory resources, and calculation time of the algorithms developed are estimated. Comparison of various variants of the algorithms is made and recommendations on their application for the development of networks-on-chip with triple loop circulant topologies are given. It is shown that Advanced clockwise and Direction selection algorithms guarantee that the packet reaches the destination node, but often in more steps than the shortest path. Nevertheless, they themselves are simpler and require less hardware resources than other algorithms. In turn, Coefficients finding algorithm has great computational complexity, but is optimal and, in comparison with Dijkstra's algorithm, is much simpler for RTL implementation which reduces network-on-chip routers resources cost.

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Design and analysis of application specific network on chip for reliable custom topology

Cited by 21 publications

References 21 publications

An efficient NoC router design by using an enhanced AES with retiming and clock gating techniques

An efficient NoC router design by using an enhanced AES with retiming and clock gating techniques

Aging-Resilient Topology Synthesis of Heterogeneous Manycore Network-On-Chip Using Genetic Algorithm with Flexible Number of Routers

Routing in triple loop circulants: A case of networks-on-chip

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