An efficient NoC router design by using an enhanced AES with retiming and clock gating techniques

Venkataraman, Natrajan; Kumar, R.

doi:10.1002/ett.3839

Cited by 7 publications

(6 citation statements)

References 27 publications

(36 reference statements)

Supporting

Mentioning

Contrasting

Order By: Relevance

“…Compared to the AES [7] that requires more than 1300 LUT-FF pairs and works at a maximum frequency of 155 MHz, the LED block cipher is much better and more efficient especially for limited resources devices such as IoT devices.…”

Section: Experiments and Resultsmentioning

confidence: 99%

See 1 more Smart Citation

Lightweight Cryptography for Network-on-Chip Data Encryption

Ayachi

Mhaouch

Abdelali

2021

Security and Communication Networks

View full text Add to dashboard Cite

System-on-chip (SoC) is the main processor for most recent applications such as the Internet of things (IoT). SoCs are composed of multiple blocks that communicate with each other through an integrated router. Data routing from a block to another poses many challenges. The network-on-chip (NoC) was used for the transmission of data from a source to a destination with high reliability, high speed, low power consumption, and low hardware occupation. An NoC is composed of a router, network links (NL), and network interface (NI). The main component of the NoC, the NI, is composed of an input/output FIFO, a finite state machine (FSM), pack, and depack modules. Data transmission from a block to another poses a security problem such as secret information extraction. In this paper, we proposed a data encryption framework for NoC based on a light encryption device (LED) algorithm. The main advantages of the proposed algorithm are to reduce the implementation area and to achieve high speed while reducing the power consumption. The proposed encryption framework was simulated Verilog/VHDL on the Xilinx ISE and implemented on the Xilinx Virtex 5 XC5VFX200T. The obtained results have shown that the proposed framework has a smaller area and higher speed compared to existing works. The proposed algorithm has reduced the NI implementation area and enhanced the network performance in terms of speed and security.

show abstract

Section: Experiments and Resultsmentioning

confidence: 99%

“…An NoC encryption solution based on the AES was proposed in [7]. To reduce the implementation area of the proposed AES, a custom C-S-box was proposed.…”

Section: Related Workmentioning

confidence: 99%

Lightweight Cryptography for Network-on-Chip Data Encryption

Ayachi

Mhaouch

Abdelali

2021

Security and Communication Networks

View full text Add to dashboard Cite

show abstract

“…A router can be considered as the backbone of NoC (Venkataraman and Kumar, 2019;Yan and Sridhar, 2018), as NoC is a network of routers connected together (Darbandi et al, 2020), therefore, it is implied that an efficient router will result in an efficient NoC as well (Monfared and Mousavi, 2020;Kale and Gaikwad, 2011). Thus, adoption of a right routing methodology is one of the most important components of NoC (Chabok and Alavi, 2020).…”

Section: Introductionmentioning

confidence: 99%

Adaptive hybrid arbiter design for real-time traffic-aware scheduling

Khan

Mir

Din

2021

View full text Add to dashboard Cite

Purpose This work focused on a basic building block of an allocation unit that carries out the critical job of deciding between the conflicting requests, i.e. an arbiter unit. The purpose of this work is to implement an improved hybrid arbiter while harnessing the basic advantages of a matrix arbiter. Design/methodology/approach The basic approach of the design methodology involves the extraction of traffic information from buffer signals of each port. As the traffic arrives in the buffer of respective ports, information from these buffers acts as a source of differentiation between the ports receiving low traffic rates and ports receiving high traffic rates. A logic circuit is devised that enables an arbiter to dynamically assign priorities to different ports based on the information from buffers. For implementation and verification of the proposed design, a two-stage approach was used. Stage I comprises comparing the proposed arbiter with other arbiters in the literature using Vivado integrated design environment platform. Stage II demonstrates the implementation of the proposed design in Cadence design environment for application-specific integrated chip level implementation. By using such a strategy, this study aims to have a special focus on the feasibility of the design for very large-scale integration implementation. Findings According to the simulation results, the proposed hybrid arbiter maintains the advantage of a basic matrix arbiter and also possesses the additional feature of fault-tolerant traffic awareness. These features for a hybrid arbiter are achieved with a 19% increase in throughput, a 1.5% decrease in delay and a 19% area increase in comparison to a conventional matrix arbiter. Originality/value This paper proposes a traffic-aware mechanism that increases the throughput of an arbiter unit with some area trade-off. The key feature of this hybrid arbiter is that it can assign priorities to the requesting ports based upon the real-time traffic requirements of each port. As a result of this, the arbiter is dynamically able to make arbitration decisions. Now because buffer information is valuable in winning the priority, the presence of a fault-tolerant policy ensures that none of the priority is assigned falsely to a requesting port. By this, wastage of arbitration cycles is avoided and an increase in throughput is also achieved.

show abstract

“…The computational time (CT) of the hardware architecture is reduced using a retiming concept. 27 FPGA implementation and ASIC synthesis of proposed retimed IIR filter architecture are also carried out, for which the CT is significantly improved by 39 to 43 and 120 to 133 times, respectively. A comparative analysis is further carried out with two existing benchmark literature.…”

Section: Introductionmentioning

confidence: 99%

“…Based on these parameters, both hardware implementation and MATLAB simulation results show the comparable accuracy. The computational time (CT) of the hardware architecture is reduced using a retiming concept 27 . FPGA implementation and ASIC synthesis of proposed retimed IIR filter architecture are also carried out, for which the CT is significantly improved by 39 to 43 and 120 to 133 times, respectively.…”

Section: Introductionmentioning

confidence: 99%

Hardware implementation of infinite impulse response anti‐notch filter for exon region identification in eukaryotic genes

Pathak

Nanda

Joshi

et al. 2020

Circuit Theory & Apps

View full text Add to dashboard Cite

The discrimination of exons from introns in the DNA sequence of a eukaryotic gene is important to understand the functionality of protein formation inside a living organism. Several signal processing techniques involving transforms and filtering have been used to identify the exon regions by exploring the periodicity-3 property. Fast processing of massive DNA sequences is desirable to detect the disease-causing mechanism, which is helpful to prepare individual-centric drugs. In this manuscript, a hardware implementation is carried out for the direct form-II structure of the infinite impulse response anti-notch filter to achieve the fast processing of the DNA sequence. Implementation result on Zynq-series (Zybo board) Field Programmable Gate Array (FPGA) reveals that the proposed implementation is capable to identify the exon regions of five benchmark eukaryotic genes. The FPGA implementation has achieved a maximum clock frequency of 34.629 MHz, which is further improved to 54.41 MHz using the retiming concept. Compared with MATLAB 2014a simulation, the proposed FPGA implementation has achieved similar accuracy with 39 to 43 times faster computing time for the five benchmark data sets. Further, an Application Specific Integrated Circuit (ASIC) implementation is carried out in the CADENCE Register Transfer Level (RTL) compiler tool with GPDK 90-nm technology, due to which the hardware antinotch filter is 120 to 133 times faster compared with its MATLAB counterpart while maintaining the comparable accuracy.

show abstract

An efficient NoC router design by using an enhanced AES with retiming and clock gating techniques

Cited by 7 publications

References 27 publications

Lightweight Cryptography for Network-on-Chip Data Encryption

Lightweight Cryptography for Network-on-Chip Data Encryption

Adaptive hybrid arbiter design for real-time traffic-aware scheduling

Hardware implementation of infinite impulse response anti‐notch filter for exon region identification in eukaryotic genes

Contact Info

Product

Resources

About