Router architecture for high-performance NoCs

Abstract

A considerable number of NoC designs are available, focusing on different aspects of this type of communication infrastructure. Example of relevant aspects considered during NoC design are quality-of-service achievement, the choice of synchronization method to employ between routers, power consumption reduction and application modules mapping. However, some design choices are common to many if not most NoC proposals: wormhole packet switching and the use of virtual channels. This work discusses trade-offs on using circuit and packet switching, arguing in favor of the former with fixed packet size. Next, it proposes and justifies the replacement of virtual channels by replicated channels, based on the abundance of wires expected in current and future deep sub-micron technologies. Finally, the work proposes the use of a session layer coupled to circuit switching. Results point out to reduced latency and router area, leading to a router architecture adapted for high-performance NoCs.

Design of NoC Router Architecture using VHDL

“…7. Here table I shows the comparison of proposed router with other routers [15,16,17]. The operating frequency of this router is 210.631MHz.…”

“…It is hard to do the comparison directly with other works, so the router area and the frequency of the proposed router are considered for comparison with the other works [15, 16, and 17]. Everton Carara et al [15], Moraes et al [16] presented the replicated channel router and virtual channel router which uses switch control for arbitration and Swapna S et al [17] presented the router with FIFO registers and scheduler which uses round robin algorithm. The virtual channel buffers used in this router provides better channel utilization as well as this router has low latency and requires less area as compare to other routers.…”

Floorplan-Aware High Performance NoC Design

“…This has been inherited from the off-chip domain [49]. Carara et al [50] reuse this concept for NoCs. In particular, they take advantage of the abundance of wires in current and expected deep sub-micron technologies.…”

“…Some of these modify switch pipelining shown in Figure 3.1(b) by performing some stages in parallel. In contrast, other proposals modify the whole switch architecture [44,50,53]. In general, switch optimization efforts lie on improving switch performance measured as throughput or latency at the expense of increasing the complexity of the switch.…”

High Performance and Power Efficient On-Chip Network Designs through Multiple Injection Ports

“…Examples are [28] and [4]. In the first work, authors propose multiplane virtual-channel router which has multiple crossbar switches and a modified switch allocator is proposed to enhance the latency and throughput performance.…”