2017 Symposium on VLSI Technology 2017
DOI: 10.23919/vlsit.2017.7998170
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The first GeSn FinFET on a novel GeSnOI substrate achieving lowest S of 79 mV/decade and record high Gm, int of 807 μS/μm for GeSn P-FETs

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Cited by 26 publications
(20 citation statements)
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“…GeSn has an extremely high carrier mobility, so it may also be an ideal materials for transistor applications. Due to the significant development of GeSn CVD growth technology, vertically stacked 3-GeSn-nanosheet pGAAFETs (gate-all-around FETs) [ 91 ], GeSn p-FinFETs [ 92 , 93 ], GeSn n-channel MOSFETs [ 94 , 95 ], GeSn/Ge vertical nanowire pFETs [ 96 ], GeSn GAA nanowire pFETs [ 97 ], and GeSn n-FinFETs [ 98 ] have been successfully demonstrated. Additionally, GeSn’s direct band gap property was found to effectively improve the tunneling probability of electrons, making an excellent material for TFET preparation [ 99 , 100 ], this opening a new development direction for the integrated circuit after Moore’s era.…”
Section: Introductionmentioning
confidence: 99%
“…GeSn has an extremely high carrier mobility, so it may also be an ideal materials for transistor applications. Due to the significant development of GeSn CVD growth technology, vertically stacked 3-GeSn-nanosheet pGAAFETs (gate-all-around FETs) [ 91 ], GeSn p-FinFETs [ 92 , 93 ], GeSn n-channel MOSFETs [ 94 , 95 ], GeSn/Ge vertical nanowire pFETs [ 96 ], GeSn GAA nanowire pFETs [ 97 ], and GeSn n-FinFETs [ 98 ] have been successfully demonstrated. Additionally, GeSn’s direct band gap property was found to effectively improve the tunneling probability of electrons, making an excellent material for TFET preparation [ 99 , 100 ], this opening a new development direction for the integrated circuit after Moore’s era.…”
Section: Introductionmentioning
confidence: 99%
“…Based on the GeSnOI platform, a GeSn FinFET has been reported. The schematic diagram of the device structure is shown in Figure 2 i [ 56 ]. The scanning electron microscopy (SEM) image of the device is shown in Figure 2 j [ 56 ].…”
Section: Fabrication Of Si- and Ge-based Thin Film-on-insulators Via Wafer Bonding Methodsmentioning
confidence: 99%
“…The schematic diagram of the device structure is shown in Figure 2 i [ 56 ]. The scanning electron microscopy (SEM) image of the device is shown in Figure 2 j [ 56 ]. The channel lengths and fin width are down to 50 nm and 20 nm, respectively.…”
Section: Fabrication Of Si- and Ge-based Thin Film-on-insulators Via Wafer Bonding Methodsmentioning
confidence: 99%
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