The energy driven paradigm of nMOSFET hot carrier effects

Rauch, Sebastian; Rosa, G. La

doi:10.1109/relphy.2005.1493216

Cited by 33 publications

(28 citation statements)

References 9 publications

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“…In addition to PBTI, such as the access transistors in a SRAM cell, also suffer from hot carrier aging (HCA) [14]. As channel length down-scales, HCA scales up and has attracted many attentions recently [14][15][16][17]. It has been reported that ETs contribute substantially to HCA, especially under Vg=Vd [16].…”

Section: Introductionmentioning

confidence: 99%

Insight Into Electron Traps and Their Energy Distribution Under Positive Bias Temperature Stress and Hot Carrier Aging

Duan

Zhang

et al. 2016

IEEE Trans. Electron Devices

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Abstract-The access transistor of SRAM can suffer both Positive Bias Temperature Instability (PBTI) and Hot Carrier Aging (HCA) during operation. The understanding of electron traps (ETs) is still incomplete and there is little information on their similarity and differences under these two stress modes. The key objective of this paper is to investigate ETs in terms of energy distribution, charging and discharging properties, and generation. We found that both PBTI and HCA can charge ETs which center at 1.4eV below conduction band (Ec) of high-k (HK) dielectric, agreeing with theoretical calculation. For the first time, clear evidences are presented that HCA generates new ETs, which do not exist when stressed by PBTI. When charged, the generated ETs' peak is 0.2eV deeper than that of pre-existing ETs. In contrast with the power law kinetics for charging the pre-existing ETs, filling the generated ETs saturates in seconds, even under an operation bias of 0.9 V. ET generation shortens device lifetime and must be included in modelling HCA. A cyclic and anti-neutralization ETs model (CAM) is proposed to explain PBTI and HCA degradation, which consists of pre-existing cyclic electron traps (PCET), generated cyclic electron traps (GCET), and anti-neutralization electron traps (ANET).

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Section: Introductionmentioning

confidence: 99%

Insight Into Electron Traps and Their Energy Distribution Under Positive Bias Temperature Stress and Hot Carrier Aging

Duan

Zhang

et al. 2016

IEEE Trans. Electron Devices

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“…In this context, the degradation of the transistor under HC stress cannot be studied anymore at the so called ''worst case'' stress condition (as formerly proposed in [1]), but must cover all Vg/Vd working conditions (as presented in [2]). The study of new stress conditions has evidenced new degradation phenomena (such as Electron Electron Scattering, EES, or Multiple Vibrational Excitation, MVE), whose non trivial understanding (see [2][3][4][5]) requires to analyze the degradation at a microscopic scale. In this work, we will analyze the macroscopic HC degradation modeling's capability to reproduce the degradation, in a first part, and then propose a microscopic HC degradation modeling, validated with measurements, which allows gaining a better understanding of the degradation of a transistor.…”

Section: Introductionmentioning

confidence: 99%

Microscopic scale characterization and modeling of transistor degradation under HC stress

Randriamihaja

Huard

Federspiel

et al. 2012

Microelectronics Reliability

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“…A process of electrons tunnel through a barrier in the presence of a high electric field was taken into account by using Fowler-Nordheim model. While, the lucky-electron model provides an estimate of the probability that some carriers in silicon will be transmitted to the oxide by overcoming the local energy barrier at the Si-SiO2 interface [7][8][9]. We also compared HCI results of our proposed nLDMOS structure with silicon HCI results for other nLDMOS device and we achieved better HCI results as compared to Silicon HCI results.…”

Section: Xquhvwulfwhg Xvhmentioning

confidence: 90%

Study of impact of LATID on HCI reliability for LDMOS devices

Sheu

Yang

Chien

et al. 2016

MATEC Web of Conferences

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Abstract. This paper demonstrates electrical degradation due to Hot Carrier Injection (HCI) stress for nLDMOS devices with different Large Angle Tilted Implantation Doping (LATID) techniques for p-body. It seems that optimization of the device with LATID angle for p-body in nLDMOS is important to achieve improved HCI performance and observed that HCI degradation is minimum for 30 0 LATID for p-body. We observed Si/SiO2 interface trap under various stress conditions, were evaluation based on our Sentaurus simulation, and we compare trapped charge density and distribution for various LATID angles and it was less for 30 0 tilt. Trap-related models were employed to perform Ron and Id,sat degradations during the HCI stress test. So nLDMOS device with 30 0 tilt angle for p-body shows better HCI performance compared to other LATID. Also our new proposed device structure shows less HCI degradations when compared with silicon data of HCI degradations for other nLDMOS structure.

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The energy driven paradigm of nMOSFET hot carrier effects

Cited by 33 publications

References 9 publications

Insight Into Electron Traps and Their Energy Distribution Under Positive Bias Temperature Stress and Hot Carrier Aging

Insight Into Electron Traps and Their Energy Distribution Under Positive Bias Temperature Stress and Hot Carrier Aging

Microscopic scale characterization and modeling of transistor degradation under HC stress

Study of impact of LATID on HCI reliability for LDMOS devices

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