The Effect of Layout Topology on Single-Event Transient Pulse Quenching in a 65 nm Bulk CMOS Process

Ahlbin, J. R.; Gadlage, Matthew J.; Ball, D. R.; Witulski, A W; Bhuva, B. L.; Reed, Robert A.; Vizkelethy, György; Massengill, L.W.

doi:10.1109/tns.2010.2085449

Cited by 69 publications

(46 citation statements)

References 16 publications

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“…6 gives insight into the generation of DPSETs by separating out the pulse widths of each event. The first pulse has a typical distribution of pulse widths similar to previously reported SET pulse width distributions for particles at normal incidence [11] [12], and would indicate that the ion is passing through the drain region of the pMOS transistor. The first pulse has a wider distribution spanning from 25 ps to 275 ps, whereas the second pulse, has a narrower distribution of pulse widths from 50 ps to 175 ps.…”

Section: Dpset Experimental Resultssupporting

confidence: 76%

Double-pulse-single-event transients in combinational logic

Ahlbin

Loveless

Ball

et al. 2011

2011 International Reliability Physics Symposium

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For the first time, double-pulse-single-event transients (DPSETs) are observed during heavy-ion broad beam testing. The transients are generated in a serially connected string of inverters and measured with an autonomous on-chip SET pulse-width measurement circuit. Three-dimensional mixed-mode technology computer aided design (TCAD) simulations show that DPSETs are the result of multiple inverters being upset by a single ion strike.

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Section: Dpset Experimental Resultssupporting

confidence: 76%

Double-pulse-single-event transients in combinational logic

Ahlbin

Loveless

Ball

et al. 2011

2011 International Reliability Physics Symposium

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“…The parasitic bipolar effect is an additional effect that involves charge draining after a charged ion strike [12], [65], [66], [71], [74], [75]. Parasitic bipolar effect is the process where a PMOS transistor's junction between the P+ source and the N-well is forward biased, resulting in a P-N-P parasitic bipolar junction transistor through the PMOS substrate to be turned on.…”

Section: Parasitic Bipolar Based Equalization Mechanismmentioning

confidence: 99%

Single Event Transients and Pulse Quenching Effects in Bandgap Reference Topologies for Space Applications

Andreou

Javanainen

Rominski

et al. 2016

IEEE Trans. Nucl. Sci.

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Abstract-An architectural performance comparison of bandgap voltage reference variants, designed in a 0.18 µm CMOS process, is performed with respect to single event transients. These are commonly induced in microelectronics in the space radiation environment. Heavy ion tests (Silicon, Krypton, Xenon) are used to explore the analog single-event transients and have revealed pulse quenching mechanisms in analogue circuits. The different topologies are compared, in terms of cross-section, pulse duration and pulse amplitude. The measured results, and the explanations behind the findings, reveal important guidelines for designing analog integrated circuits, which are intended for space applications. The paper includes an analysis on how pulse quenching occurs within the indispensable current mirror, which is used in every analog circuit.

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“…The SET pulses widths were extracted from [8] and [9], where pulses duration distributions are presented, as function of the LET, on a CMOS 65nm technology. In order to highlight the effect of SET fault injection, 3 different pulses widths, 75, 150 and 300 ps were applied.…”

Section: Fault Injection Predictionmentioning

confidence: 99%