The cat and mouse in split manufacturing

Wang, Yujie; Chen, Pu; Hu, Jiang; Rajendran, Jeyavijayan

doi:10.1145/2897937.2898104

Cited by 68 publications

(128 citation statements)

References 15 publications

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“…Compared with the state-ofthe-art network-flow attack [1], the correct connection rate is improved by 1.21× and 1.12× when splitting on Metal 1 and Metal 3, respectively. Moreover, the runtime for our attack is significantly less, namely less than 1% of that of [1]. As a part of future work, we plan to extend our neural network to tackle industrial layouts which have been incorporated with various placement-based and/or routing-based defense strategies.…”

Section: Resultsmentioning

confidence: 94%

Attacking Split Manufacturing from a Deep Learning Perspective

Patnaik²,

Sengupta³

et al. 2019

Proceedings of the 56th Annual Design Automation Conference 2019

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The notion of integrated circuit split manufacturing which delegates the front-end-of-line (FEOL) and back-end-of-line (BEOL) parts to different foundries, is to prevent overproduction, piracy of the intellectual property (IP), or targeted insertion of hardware Trojans by adversaries in the FEOL facility. In this work, we challenge the security promise of split manufacturing by formulating various layout-level placement and routing hints as vector-and imagebased features. We construct a sophisticated deep neural network which can infer the missing BEOL connections with high accuracy. Compared with the publicly available network-flow attack [1], for the same set of ISCAS-85 benchmarks, we achieve 1.21× accuracy when splitting on M1 and 1.12× accuracy when splitting on M3 with less than 1% running time.

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Section: Resultsmentioning

confidence: 94%

Attacking Split Manufacturing from a Deep Learning Perspective

Patnaik²,

Sengupta³

et al. 2019

Proceedings of the 56th Annual Design Automation Conference 2019

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“…A network-flow based attack model towards flattened designs was proposed by Wang et. al [20]. The authors argued that the proximity attack originally proposed by [10] utilizes hints that can be used only by hierarchical designs, and that modern designs are often flattened 3 .…”

Section: Attacks On Split Manufacturingmentioning

confidence: 99%

“…The EMSR metric is an attempt to quantify the ratio of real gates location of a given mapping during a simulated annealing-based attack. This defense consists of two steps, first a greedy gate swapping defense [20], and second, a measurement of the security elevation in terms of EMSR. The technique is evaluated using ISCAS'85 benchmarks circuits and the EMSR metric to quantify the defense effectiveness.…”

Section: A Proximity Perturbationmentioning

confidence: 99%

A Survey on Split Manufacturing: Attacks, Defenses, and Challenges

Perez

Pagliarini

2020

IEEE Access

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In today's integrated circuit (IC) ecosystem, owning a foundry is not economically viable, and therefore most IC design houses are now working under a fabless business model. In order to overcome security concerns associated with the outsorcing of IC fabrication, the Split Manufacturing technique was proposed. In Split Manufacturing, the Front End of Line (FEOL) layers (transistors and lower metal layers) are fabricated at an untrusted high-end foundry, while the Back End of Line (BEOL) layers (higher metal layers) are manufactured at a trusted low-end foundry. This approach hides the BEOL connections from the untrusted foundry, thus preventing overproduction and piracy threats. However, many works demonstrate that BEOL connections can be derived by exploiting layout characteristics that are introduced by heuristics employed in typical floorplanning, placement, and routing algorithms. Since straightforward Split Manufacturing may not afford a desirable security level, many authors propose defense techniques to be used along with Split Manufacturing. In our survey, we present a detailed overview of the technique, the many types of attacks towards Split Manufacturing, as well as possible defense techniques described in the literature. For the attacks, we present a concise discussion on the different threat models and assumptions, while for the defenses we classify the studies into three categories: proximity perturbation, wire lifting, and layout obfuscation. The main outcome of our survey is to highlight the discrepancy between many studiessome claim netlists can be reconstructed with near perfect precision, while others claim marginal success in retrieving BEOL connections. Finally, we also discuss future trends and challenges inherent to Split Manufacturing, including the fundamental difficulty of evaluating the efficiency of the technique.

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“…Another recent approach towards trustworthy chips is split manufacturing [124], [135], [140], [155], [156], [157], [158], [159], [160], [161], [162]. It seeks to prevent the insertion of Trojans and/or the theft of IP in the first place.…”

Section: Split Manufacturingmentioning

confidence: 99%

“…To the untrusted FEOL party, the outsourced design parts merely appear as a "sea of gates," where the missing interconnects may prevent one from (i) inferring any of the actual functionality and/or (ii) localizing particular circuitry prone or fruitful for Trojan attacks. How exactly such splitting can be rendered truly secure yet practical (in terms of reasonably low manufacturing and layout-level cost) is currently still under broad and vivid investigation [155], [156], [157], [159], [160], [161].…”

Section: Split Manufacturingmentioning

confidence: 99%

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

Knechtel

Sinanoglu

Elfadel

et al. 2017

IPSJ Transactions on System LSI Design Methodology

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Three-dimensional (3D) integration of electronic chips has been advocated by both industry and academia for many years. It is acknowledged as one of the most promising approaches to meet ever-increasing demands on performance, functionality, and power consumption. Furthermore, 3D integration has been shown to be most effective and efficient once large-scale integration is targeted for. However, a multitude of challenges has thus far obstructed the mainstream transition from "classical 2D chips" to such large-scale 3D chips. In this paper, we survey all popular 3D integration options available and advocate that using an interposer as system-level integration backbone would be the most practical for large-scale industrial applications and design reuse. We review major design (automation) challenges and related promising solutions for interposer-based 3D chips in particular, among the other 3D options. Thereby we outline (i) the need for a unified workflow, especially once full-custom design is considered, (ii) the current design-automation solutions and future prospects for both classical (digital) and advanced (heterogeneous) interposer stacks, (iii) the state-of-art and open challenges for testing of 3D chips, and (iv) the challenges of securing hardware in general and the prospects for large-scale and trustworthy 3D chips in particular.

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The cat and mouse in split manufacturing

Cited by 68 publications

References 15 publications

Attacking Split Manufacturing from a Deep Learning Perspective

Attacking Split Manufacturing from a Deep Learning Perspective

A Survey on Split Manufacturing: Attacks, Defenses, and Challenges

Large-Scale 3D Chips: Challenges and Solutions for Design Automation, Testing, and Trustworthy Integration

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