The architectures and design of a 20-MHz real-time DSP chip set

An efficient FIR filter architecture

“…The custom implementation is substantially smaller (by a factor of approximately two and a half) than the equivalent filter based on full two's complement multipliers and adders. The area/speed performance of this design compares favorably with those in [5,12,16,18,19] when normalized for the older technology used in the present case. In particular, the architecture in [19], based on the FIRGEN compiler [8], also uses canonic signed-digit (CSD) coefficients.…”

Anatomy of a Silicon Compiler

“…These require varying amounts of hardware complexity and in many cases rely on heavily pipelining the architecture since pipeline latency can be introduced in FIR structures without affecting the input/output transfer function. However, the use of indiscriminate pipelining leads to substantial increases in power dissipation as well as chip area due to the pipeline registers [Reutz89,Jain87]. The increase in power dissipation is of special concern at high speeds.…”

New Cost-effective VLSI Implementation of Multiplierless FIR Filter using Common Subexpression Elimination

“…The term (log 1.5 N ) × T a is the delay through an adder tree structure (see, e.g. [9] and [10]). This equation includes only arithmetic critical path delay in the architecture.…”

“…In the actual VLSI design, RC delay due to layout parasitics needs to be taken into consideration. Table. IV summarizes the maximum logical depth (LD) of multiplier block and the critical path delay (T m ) given in Equation (9). T d is estimated to be T d = 0.1T a provided that the FIR filter is fabricated in a 0.35 µm standard CMOS process.…”