An efficient FIR filter architecture

Evans, J.B.

doi:10.1109/iscas.1993.692722

Cited by 6 publications

(1 citation statement)

References 7 publications

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“…An efficient architecture for FIR filters has been described in [38], which shows reduced complexity by use of sparse powers of two coefficients. FIR filter is implemented here by using two full adders and two latches which are implemented on FPGA.…”

Section: Literature Reviewmentioning

confidence: 99%

Vedic Mathematics for Digital Signal Processing Operations: A Review

Gaikwad¹,

Chavan²

2015

IJCA

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Speed improvement in Digital signal processing is considered to be challenging. High speed multipliers and adders are prime requirement for digital filters and for FFT operations.Vedic mathematics is an ancient scheme based on 16 formulas (sutras). These are simple and easy methods which can be directly applied for DSP computations. Many researchers have worked on multiplier designs using Vedic operators. Present paper deals with exhaustive review of literature based on Vedic mathematics. It shows that Vedic mathematics can be used for fast signal processing. Multipliers based on Vedic mathematics can be used for speed improvement, reduction in power consumption, complexity, area etc. Vedic mathematical algorithms can be proved efficient over traditional (existing) methods in FIR and IIR filters for providing effective results in de-noising of biomedical Signal.

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Section: Literature Reviewmentioning

confidence: 99%

Vedic Mathematics for Digital Signal Processing Operations: A Review

Gaikwad¹,

Chavan²

2015

IJCA

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Implementation of programmable multiplierless FIR filters with powers-of-two coefficients

Lee

1995

IEEE Trans. Circuits Syst. II

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Automatic implementation of FIR filters on field programmable gate arrays

Mohanakrishnan

Evans

1995

IEEE Signal Process. Lett.

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This paper describes a CAD system for automatic implementation of FIR filters on Xilinx Field Programmable Gate Arrays. Given the frequency specifications, this software package designs an FIR filter, optimizes the filter coefficients in the power of two coefficient space and implements it on an FPGA chip. The FPGA specific mapping techniques used to increase speed are discussed. The performance of the typical filters which were implemented is presented.

show abstract

An efficient FIR filter architecture

Cited by 6 publications

References 7 publications

Vedic Mathematics for Digital Signal Processing Operations: A Review

Vedic Mathematics for Digital Signal Processing Operations: A Review

Implementation of programmable multiplierless FIR filters with powers-of-two coefficients

Automatic implementation of FIR filters on field programmable gate arrays

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