Vedic Mathematics for Digital Signal Processing Operations: A Review

Gaikwad, Kaustubh; Chavan, Mahesh S.

doi:10.5120/19924-1503

Cited by 7 publications

(3 citation statements)

References 28 publications

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“…They compare performance characteristics like power consumption and response time to existing designs. Gaikwad and Chavan [9] present a brief review of the Vedic techniques in Digital Signal Processing Operations.…”

Section: Application Of Vedic Mathematics In Modern Timementioning

confidence: 99%

An Overview of the Ancient Indian Vedic Mathematics Techniques

Kumari¹

2022

IJRASET

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This study examined at how Vedic Mathematics solves basic math problems using Vedic Mathematics. The ancient approach of Indian mathematics is known as Vedic mathematics. It employs a one-of-a-kind computation method based on the 16 sutras and 13 sub-sutras including a variety of modern mathematical problems such as trigonometry, arithmetic, geometry, factorization, quadratic equations, and calculus. This study summarizes some important sutras from Vedic mathematics with examples. Additionally, we highlight some recent applications of Vedic mathematics from existing literature.

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Section: Application Of Vedic Mathematics In Modern Timementioning

confidence: 99%

An Overview of the Ancient Indian Vedic Mathematics Techniques

Kumari¹

2022

IJRASET

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“…They are also applicable to complex problems involving a large number of mathematical operations. The technique has been used in various domains including the design of low‐power image compression [2] and in signal processing domain [3, 4]. The application of a Vedic multiplier in encryption/decryption algorithm, Infinite Impulse Response (IIR) filters, and floating‐point mathematics has been explored in the literature [5, 6].…”

Section: Introductionmentioning

confidence: 99%

Gate diffusion input based 4‐bit Vedic multiplier design

Garg

Joshi

2018

IET Circuits, Devices & Systems

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A multiplier is one of the key hardware blocks in most of the processors. Multiplication is a lengthy, time-consuming task. Vedic multiplication in field programmable gate array implementation has been proven effective in reducing the number of steps and circuit delay. Conventionally at the circuit level, complementary metal oxide semiconductor (CMOS) logic is used to design a multiplier. In CMOS circuits, the area is always an issue. Gate diffusion input (GDI)-based logic has been explored in the literature to reduce the number of transistors for various logic functions. Thus, Vedic mathematics, on the one hand, simplifies the multiplication process and reduces the delay; while on the other hand, GDI technique helps in minimising the transistor count (TC) and reduction in power. Therefore, this study puts forth a GDI logic-based 4-bit Vedic multiplier. To study the effectiveness of the GDI logic, the transient response of a 2-bit Vedic multiplier using CMOS and GDI is compared. For the 4-bit Vedic multiplier, two design approaches are taken into consideration. The performance of these circuits is analysed in terms of average power dissipation, delay, and TC. The effect of supply voltage scaling is also studied. The circuit simulations are carried out at 130 nm for bulk metal oxide semiconductor field effect transistor predictive technology model-based device parameters.

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“…processor speed, high resolution, slicing the components of image etc. Hence, in this regards, we came across the evolution of Vedic mathematics and its potential application that can be readily applicable in signal processing [3], [4]. The principle of Vedic mathematics is based on the 16 principle that are originally termed as Sutra [5].…”

Section: Introductionmentioning

confidence: 99%

Design of Multiplier for Medical Image Compression Using Urdhava Tiryakbhyam Sutra

Suma

Sridhar

2016

IJECE

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Compressing the medical images is one of the challenging areas in healthcare industry which calls for an effective design of the compression algorithms. The conventional compression algorithms used on medical images doesn’t offer enhanced computational capabilities with respect to faster processing speed and is more dependent on hardware resources. The present paper has identified the potential usage of Vedic mathematics in the form of Urdhava Tiryakbhyam sutra, which can be used for designing an efficient multiplier that can be used for enhancing the capabilities of the existing processor to generate enhance compression experience. The design of the proposed system is discussed with respect to 5 significant algorithms and the outcome of the proposed study was testified with heterogeneous samples of medical image to find that proposed system offers approximately 57% of the reduction in size without any significant loss of data.

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Vedic Mathematics for Digital Signal Processing Operations: A Review

Cited by 7 publications

References 28 publications

An Overview of the Ancient Indian Vedic Mathematics Techniques

An Overview of the Ancient Indian Vedic Mathematics Techniques

Gate diffusion input based 4‐bit Vedic multiplier design

Design of Multiplier for Medical Image Compression Using Urdhava Tiryakbhyam Sutra

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