The architectures and design of a 20-MHz real-time DSP

Abstract

A set of four real-time 20-Mhz DSP chips have been designed, fabricated, and tested. The chips include a 64-tap programmable FIR filter, a 1024-tap binary filter and template matcher, a 64-tap rank-value filter, and an 8-line 512-pixel video line delay. All of the circuits were implemented in a 1 . 5~ CMOS process and are fully functional with a 20 MHz clock rate.