70-MHz 2- mu m CMOS bit-level systolic array median filter

Roncella, Roberto; Saletti, Roberto; Terreni, Pierangelo

doi:10.1109/4.229403

Cited by 23 publications

(12 citation statements)

References 14 publications

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“…Due to the non-linear nature of the median ®lter, it is highly desirable in many applications to implement median ®lters in the form of regular arrays for high performance and small area. Some of our designs are similar to those in [35], which have been implemented in 2 lm CMOS technology. Finally, we show that our median ®lter designs can be very eciently implemented in FPGAs.…”

Section: Introductionmentioning

confidence: 84%

An integrated system for developing regular array designs

Guo¹,

Luk

2001

Journal of Systems Architecture

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This paper describes an integrated system for developing regular array designs based on the block description language Ruby. Ruby supports concise design description and formal veri®cation. A parametrised Ruby description can be used in simulating, re®ning and visualising designs, and in compiling hardware implementations such as ®eld programmable gate arrays. Our system enables rapid design production, while good design quality is achieved by (a) the ecient instantiation of device-speci®c libraries, (b) the size optimisation of bit-level components using the design re®ner, and (c) the exploitation of regularity information at source level in the library composition process. The development and implementation of several median ®lters are used to illustrate the system. Ó

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Section: Introductionmentioning

confidence: 84%

An integrated system for developing regular array designs

Guo¹,

Luk

2001

Journal of Systems Architecture

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“…The unique ability of providing both low latency and high throughput makes the architecture different from those reported in the literature. The hardware complexity proportional to the window length, makes it more efficient than [12,13], and comparable to [10,11], though our solution appears simpler and can deliver the result with the latency of 2 at 1/2 of the sampling rate. clk1 and clk2 show clock cycles; Z and T denote the requests to move-left (removal) and move-right (insertion) operations, respectively.…”

Section: A Architecturementioning

confidence: 91%

“…The design is simple, compact yet efficient. Unlike existing implementations of sorting networks [10][11][12][13][14][15][16][17][18][19] that propagate the incoming samples along the window pipelines to compare and swap the samples with the values stored in the window ranks "on the fly", we do not use pipelining. In our design, all values of the window are compared with the incoming sample at once.…”

Section: Contributionmentioning

confidence: 99%

“…Furthermore, median filters can be divided into three categories: array architectures [2][3][4][5][6][7][8][9][10][11][12] sorting-network architectures [13][14][15][16][17][18] and stack-based architectures [20][21][22][23][24][25][26]. In array architectures each element of the window is associated with the rank, and with each window shift, the ranks are updated.…”

Section: B Related Researchmentioning

confidence: 99%

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An efficient implementation of 1-D median filter

Moshnyaga

Hashimoto

2009

2009 52nd IEEE International Midwest Symposium on Circuits and Systems

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This paper presents a new architecture and circuit implementation of 1-D median filter. The proposed circuit belongs to the class of non-recursive sorting network architectures that process the input samples sequentially in the word-based manner. In comparison to the related schemes, it maintains sorting of samples from the previous position of the sliding window, positioning only the incoming sample to the correct rank. Unlike existing 1-D filter implementations, the circuit has linear hardware complexity, minimal latency and achieves throughput of 1/2 of the sampling rate. Experimental evaluation and comparisons show high efficiency of our design.

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“…Variations on this approach have been described in the literature [107][108][109]. Systolic array architectures for bit-level sorting networks have been shown to improve concurrency of the bit-serial sorting designs [102,103,[110][111][112][113]. The median filter design presented in this work is a combination and 3D extension of bit-serial searching and majority voting approaches.…”

Section: Multiobjective Optimizationmentioning

confidence: 99%

High-Performance 3D Image Processing Architectures for Image-Guided Interventions

Dandekar¹

2008

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Minimally invasive image-guided interventions (IGIs) are time and cost efficient, minimize unintended damage to healthy tissues, and lead to faster patient recovery. Advanced three-dimensional (3D) image processing is a critical need for navigation during IGIs. However, achieving on-demand performance, as required by IGIs, for these image processing operations using software-only implementations is challenging because of the sheer size of the 3D images, and memory and compute intensive nature of the operations. This dissertation, therefore, is geared toward developing high-performance 3D image processing architectures, which will enable improved intraprocedural visualization and navigation capabilities during IGIs.In this dissertation we present an architecture for real-time implementation of 3D filtering operations that are commonly employed for preprocessing of medical images. This architecture is approximately two orders of magnitude faster than corresponding software implementations and is capable of processing 3D medical images at their acquisition speeds. Report Documentation PageCombining complementary information through registration between pre-and intraprocedural images is a fundamental need in the IGI workflow. Intensity-based deformable registration, which is completely automatic and locally accurate, is a promising approach to achieve this alignment. These algorithms, however, are extremely compute intensive, which has prevented their clinical use. We present an FPGA-based architecture for accelerated implementation of intensity-based deformable image registration. This high-performance architecture achieves over an order of magnitude speedup when compared with a corresponding software implementation and reduces the execution time of deformable registration from hours to minutes while offering comparable image registration accuracy.Furthermore, we present a framework for multiobjective optimization of finite-precision implementations of signal processing algorithms that takes into account multiple conflicting objectives such as implementation accuracy and hardware resource consumption. The evaluation that we have performed in the context of FPGA-based image registration demonstrates that such an analysis can be used to enhance automated hardware design processes, and efficiently identify a system configuration that meets given design constraints. In addition, we also outline two novel clinical applications that can directly benefit from these developments and demonstrate the feasibility of our approach in the context of these applications. These advances will ultimately enable integration of 3D image processing into clinical workflow.

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70-MHz 2- mu m CMOS bit-level systolic array median filter

Cited by 23 publications

References 14 publications

An integrated system for developing regular array designs

An integrated system for developing regular array designs

An efficient implementation of 1-D median filter

High-Performance 3D Image Processing Architectures for Image-Guided Interventions

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