TFT (thin film transistor) cell technology for 4 Mbit and more high density SRAMs

Kinugawa, M.; Kakumu, M.; Yoshida, Takeshi; Nakayama, Takashi; Morita, S.; Kubota, Koji; Matsuoka, F.; Oyamatsu, H.; Ochii, K.; Maeguchi, K.

doi:10.1109/vlsit.1990.110989

Cited by 9 publications

(4 citation statements)

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“…There have been many approaches to reduce the cell size of SRAM such as pseudo-SRAM [SI and TFT-SRAM [9], but they have many limitations in operating temperature, standby current and so on. One of the innovative ways to reduce cell size is to 0-7803-9081 -4/05/$20.00 02005 IEEE stack transistors vertically by adopting Stacked Singlecrystal Thin Film Transistor (SSTFT) [lo].…”

Section: Memory Technologies In the Nano-era : Challenges And Opportumentioning

confidence: 99%

Memory technologies in the nano-era : challenges and opportunities

Kim

Jeong

2005

2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005.

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There have been concerns about how far we can extend the so far so successful conventional semiconductor memories such as DRAM, SRAM and Flash memory and what will be the future directions of memory development. In this article, we will review the key technological limits of conventional memory scaling and the directions to overcome the problem. In addition, we will review the technical challenges and opportunities of emerging new memories.For the future development of conventional memories, Ihe common most critical question is at what technology node memories are no longer properly working. Though ultimate limitation of scaling has different origins for each memory, it is clear that the lifetimes of conventional memories are far shorter than that of CMOS transistor.The technological limiting factor of DRAM is cell transistor scaling. The increased doping concentration due to decreased transistor channel length is accompanied by an increase of junction leakage current, which results in severe decrease of data retention time at around 90nm technology node. This difficulty can be overcome by utilizing nonplanar cell transistors. Using Recessed Channel Array Transistor (RCAT) structure [l], we can increase the effective channel length without adding significant process complexity. For further scaling below 50nm, another breakthrough in technology is needed. Using FinFET-type cell transistors, we can control channel punch-through by adjusting the channel silicon thickness. FinFET gives superior current driving capability and DIBL characteristics comparing with conventional planar transistor or RCAT. Fig.1 shows the retention characteristics of a FinFET DRAM [Z]. Excellent DIBL characteristics enable DRAM to have the good retention characteristics. Thus FinFET will be the key solution to overcome the problems arising from dimension shrinkage and will at the same time improve transistor performance at the sub-50m technology node.The most important.technological challenge of NAND Flash memory is scaling of the floating gate. Cell to cell interference will be the most critical problem to technology scaling of NAND Flash memory. When the space between word lines becomes narrower, the programmed state of a cell can be affected by adjacent cells due to capacitive coupling between floating gates (31. This problem can be solved by using low-k dielectric material and scaling down the floating gate height. Floating gate interference coupling ratio can be reduced to about 60% by using the silicon oxide gate spacer instead of silicon nitride gate spacer. And the interference can be reduced to almost zero by the use of SONOS type Flash cell structure. Fig.2 shows an example of the FinFET SONOS cell structure [43. FinFET SONOS cells operate well and have good programming characteristics even at 30nm fin width. Furthermore, the high current driving capability of FinFET-type cell transistors can also increase the sensing signal margin of NAND Flash. We expect that SONOS cells with FinFET structure will be the solution for technology ...

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Section: Memory Technologies In the Nano-era : Challenges And Opportumentioning

confidence: 99%

Memory technologies in the nano-era : challenges and opportunities

Kim

Jeong

2005

2005 International Conference on Integrated Circuit Design and Technology, 2005. ICICDT 2005.

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“…In the last decade, polycrystalline silicon thin-film transistors (poly-Si TFTs) have received much attention, in particular, for active-matrix liquid crystal displays (AMLCDs) with on-glass peripheral circuits and 3-D integrated circuits. [1][2][3] Unlike the transistors fabricated on bulk silicon substrates, the performance of poly-Si TFTs is strongly influenced by the grain boundaries and intragranular defects. In order to improve the performance of poly-Si TFTs, the recrystallization of silicon films [4][5][6][7][8] has been widely investigated to enlarge the grain size and reduce the defect-state density in poly-Si films.…”

Section: Introductionmentioning

confidence: 99%

Thin-Film Transistors with Polycrystalline Silicon Films Prepared by Two-Step Rapid Thermal Annealing

Cheng¹,

Huang²,

Wang³

et al. 2000

Jpn. J. Appl. Phys.

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A novel two-step rapid thermal annealing (RTA) process has been developed to significantly reduce the crystallization time for the solid-phase crystallization (SPC) of amorphous silicon films. In comparison with the conventional SPC processes, it not only keeps a low thermal budget but also achieves a larger poly-Si film grain size than that obtained by one-step RTA, and even as large as that obtained by conventional furnace annealing (CFA). Furthermore, poly-Si thin-film transistors fabricated by such a novel annealing scheme possess electrical characteristics superior to those obtained by one-step RTA and comparable to those obtained by long-time CFA.

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“…There are three types of SWM bit cell structures -high resistance poly-Si load cells (Hi-R cells), full CMOS cells (Full C cells) and PMOS TFT load cells cells) which appeared in 0.5pm technologies [ 1], [2].…”

Section: Sram Cell Performance and Reliabilitymentioning

confidence: 99%

“…The discussion addresses four key issues -(1) process and transistor design compatibility, (2) performance and reliability, (3) chip cost, (4) technology driver. As a result, a guideline for the desirable embedded memory bitcells has been proposed.…”

Section: Introductionmentioning

confidence: 99%

Cell technology directions for advanced MPUs and other memory-embedded logic devices

Kinugawa

Kakumu

Proceedings of IEEE International Electron Devices Meeting

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In this paper, a guideline for optimum embedded memory structures for advanced MPUs and other memory-embedded logic devices is proposed. It is concluded that introduction of full CMOS cells is inevitable for future SRkMs operated under reduced power supply voltage conditions. Therefore, MPUs will continue to use full CMOS cells maintaining excellent process and transistor design compatibility with SRAMs. On the other hand, some advanced logic devices will use DRAM cells, since they require higher density rather than higher performance or better process compatibility.

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TFT (thin film transistor) cell technology for 4 Mbit and more high density SRAMs

Cited by 9 publications

References 0 publications

Memory technologies in the nano-era : challenges and opportunities

Memory technologies in the nano-era : challenges and opportunities

Thin-Film Transistors with Polycrystalline Silicon Films Prepared by Two-Step Rapid Thermal Annealing

Cell technology directions for advanced MPUs and other memory-embedded logic devices

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