Memory technologies in the nano-era : challenges and opportunities

Abstract

There have been concerns about how far we can extend the so far so successful conventional semiconductor memories such as DRAM, SRAM and Flash memory and what will be the future directions of memory development. In this article, we will review the key technological limits of conventional memory scaling and the directions to overcome the problem. In addition, we will review the technical challenges and opportunities of emerging new memories.For the future development of conventional memories, Ihe common most critical question is at what technology node memories are no longer properly working. Though ultimate limitation of scaling has different origins for each memory, it is clear that the lifetimes of conventional memories are far shorter than that of CMOS transistor.The technological limiting factor of DRAM is cell transistor scaling. The increased doping concentration due to decreased transistor channel length is accompanied by an increase of junction leakage current, which results in severe decrease of data retention time at around 90nm technology node. This difficulty can be overcome by utilizing nonplanar cell transistors. Using Recessed Channel Array Transistor (RCAT) structure [l], we can increase the effective channel length without adding significant process complexity. For further scaling below 50nm, another breakthrough in technology is needed. Using FinFET-type cell transistors, we can control channel punch-through by adjusting the channel silicon thickness. FinFET gives superior current driving capability and DIBL characteristics comparing with conventional planar transistor or RCAT. Fig.1 shows the retention characteristics of a FinFET DRAM [Z]. Excellent DIBL characteristics enable DRAM to have the good retention characteristics. Thus FinFET will be the key solution to overcome the problems arising from dimension shrinkage and will at the same time improve transistor performance at the sub-50m technology node.The most important.technological challenge of NAND Flash memory is scaling of the floating gate. Cell to cell interference will be the most critical problem to technology scaling of NAND Flash memory. When the space between word lines becomes narrower, the programmed state of a cell can be affected by adjacent cells due to capacitive coupling between floating gates (31. This problem can be solved by using low-k dielectric material and scaling down the floating gate height. Floating gate interference coupling ratio can be reduced to about 60% by using the silicon oxide gate spacer instead of silicon nitride gate spacer. And the interference can be reduced to almost zero by the use of SONOS type Flash cell structure. Fig.2 shows an example of the FinFET SONOS cell structure [43. FinFET SONOS cells operate well and have good programming characteristics even at 30nm fin width. Furthermore, the high current driving capability of FinFET-type cell transistors can also increase the sensing signal margin of NAND Flash. We expect that SONOS cells with FinFET structure will be the solution for technology ...