Testing 3D Stacked ICs Containing Through-Silicon Vias

Marinissen, Erik Jan

doi:10.1007/978-1-4419-7618-5_3

Cited by 3 publications

(2 citation statements)

References 33 publications

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“…Malicious software executed on the 3D-MPSoC can exploit this natural phenomenon to manipulate the data on some TSV wires. The attacks can be in the form of i) modifying data on the victim-TSV through the coupling effect of adjacent aggressor TSVs [122], ii) reduce the lifetime of the victim TSV by increasing the chance of stress cracks [123], [124] or through electromigration effects [23], and iii) corrupting transmissions by delaying or speeding up signal transitions [123].…”

Section: D Nocs Countermeasuresmentioning

confidence: 99%

A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips

et al. 2021

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Network-on-Chips (NoCs) have been widely used as a scalable communication solution in the design of multiprocessor system-on-chips (MPSoCs). NoCs manage communications between on-chip Intellectual Property (IP) cores and allow processing cores to achieve higher performance by outsourcing their communication tasks. NoC paradigm is based on the idea of resource sharing where hardware resources, including buffers, communication links, routers, etc., are shared between all IPs of the MPSoC. In fact, the data being routed by each NoC router might not be related to the router's local core. Such a utilization-centric design approach can raise security issues in MPSoCs-based designs, e.g., integrity and confidentiality of the data being routed in an NoC might be compromised by unauthorized accesses/modifications of intermediate routers. Many papers in the literature have discovered and addressed security holes of NoCs, aiming at improving the security of the NoC paradigm. However, to the best of our knowledge, there is no solid survey study on the security vulnerabilities and countermeasures for NoCs. This paper will review security threats and countermeasures proposed so far for wired NoCs, wireless NoCs, and 3D NoCs. The paper aims at giving the readers an insight into the attacks and weaknesses/strengths of countermeasures.

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Section: D Nocs Countermeasuresmentioning

confidence: 99%

A Survey on the Security of Wired, Wireless, and 3D Network-on-Chips

et al. 2021

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“…Moreover, the semiconductor industry is continuously demanding more functionality, bandwidth, and performance at smaller sizes, power dissipation, and cost. Thus, TSV-based 3D-SICs are the promising solution for such requirements [3]. 3D-SICs is a continuation of Moore's Law, which is called more than Moore's law.…”

Section: Introductionmentioning

confidence: 99%

Approximate TSV-based 3D Stacked Integrated Circuits by Inexact Interconnects

Masadeh¹

2022

IJACSA

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Three-Dimensional Stacked Integrated Circuit (3D-SICs) based on Through-Silicon Vias (TSVs) provide a highdensity integration technology. However, integrating pre-tested dies requires post-bond interconnect testing, which is complex and costly. An imperfect TSV-based interconnect indicates a defective chip that should be rejected. Thus, it increases the yield loss and test cost. On the other hand, approximate computing (AC) is a promising design paradigm suitable for errorresilient applications, e.g., processing sensory-generated data, by judiciously sacrificing output accuracy. AC perform inexact operations and accepts inexact data. Thus, introducing AC into 3D-SICs will significantly ameliorate the efficiency of design approximation. Therefore, this work aims to increase the yield and reduce the test cost by accepting 3D-SICs with defected interconnects as approximate 3D-SICs. This work considers 3D-SICs, where the sensor is stacked on logic (CPU) which is stacked on memory (DRAM). Then, use the memory-based interconnect testing (MBIT) approach to detect and diagnose the faulty interconnect. Based on the detected fault location and type, and for a maximum allowed error, some sensory 3D-SICs with defected LSBs interconnects are accepted and used in errorresilient and data-intensive applications. Targeting data lines only, 50% of the defected interconnects, i.e., least significant bits (LSBs), were accepted as approximate. Thus, the proposed work was able to significantly increase the yield. Two applications, i.e., ECG signal compression and detecting of their R peaks, demonstrated the effectiveness of using a sensory device with a faulty data line in its least significant 8-bits. The approximate ECG signals have a compression rate higher than the exact with negligible (around 0.1%) reduced accuracy.

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