Temperature effects on trigate SOI MOSFETs

High temperature study of flexible silicon-on-insulator fin field-effect transistors

“…The reduction of the transconductance peak in Figure 4 as a function of the temperature is explained by the mobility lowering due to increased phonon scattering at elevated temperatures. 8,9 Further, to confirm our results with a quantitative analysis, the extracted l 0 of the FinFETs is shown in Figure 5. The low-field mobility is extracted in linear regime (V ds ¼ À0.05 V) using the Y ¼ I ds /(g m ) 1/2 function method.…”

“…The decrease of threshold voltage (V th ) with temperature tends to increase drain current, while the reduction of mobility due to increase of phonon scattering with temperature tends to decrease drain current, same as in a conventional MOSFET. 8,9 The compensation of these opposing effects at V gs ¼ À0.8 V and at V gs ¼ À0.9 V for long and short devices, respectively, leads to unique points in the characteristics with zero temperature coefficient (ZTC). Inset of Figure 2(a) shows the output characteristics (I ds -V ds ) of long and short FinFETs at 25 C and at 150 C. These curves clearly show that the drive current of the FinFETs decreases with temperature as expected without any significant degradation after release.…”

“…The subthreshold swing (SS) increases in all devices as temperature increases. 9 In addition, we plotted the I gs as a function of V gs (inset of Figure 2(b)) where the gate current increases with temperature and the variation after release sustains the nA values range. Figure 2 confirms an insignificant variation of drain current, gate-current, threshold voltage, and the subthreshold swing at high and low temperatures.…”

N-channel field-effect mobility inversely proportional to the interface state density at the conduction band edges of SiO2/4H-SiC interfaces

“…3) and that of Si MOSFETs. 17 The slopes for the Si-and C-faces increased dramatically with decreasing temperature, while the slope for the a-face remained at the same level. The subthreshold slopes at the different temperatures reflect D IT at different energies, and evaluation of the subthreshold slope at room temperature alone is insufficient to reveal the overall interface characteristics.…”

“…[1][2][3][4][5][6][7][8][9][10] Although the interface states have been assumed to be a main cause of the low channel current, 2,3,6,7,10,16 a clear correlation between the interface state density (D IT ) and the channel performance has not been determined. 11 We recently showed that the peak n-channel field-effect mobility (µ FE,peak ) at room temperature is roughly inversely proportional to D IT for samples on the (0001), (000-1), and (11)(12)(13)(14)(15)(16)(17)(18)(19)(20) faces (the Si-, C-, and a-faces, respectively) after dry/nitridation and pyrogenic/hydrotreatment processes, 12 where D IT was evaluated by the C−ψ S method 13 at 0.2 eV below the conduction band edge (E C −E T = 0.2 eV) using MOS capacitors. However, µ FE,peak for a-face MOSFETs is higher than those for the Si-and C-face MOSFETs at the same D IT .…”