Temperature Dependence of MCU Sensitivity in 65 nm CMOS SRAM

Boruzdina, Anna B.; Sogoyan, A. V.; Smolin, Anatoly A.; Ulanova, Anastasia V.; Gorbunov, Maxim S.; Chumakov, A. I.; Boychenko, Dmitry V.

doi:10.1109/tns.2015.2499120

Cited by 25 publications

(5 citation statements)

References 23 publications

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“…The guard ring (n/p-doped area) surrounding well and substrate regions (p/n-doped areas) forms parasitic bipolar transistor with base tied to keep the parasitic transistor in "close" state. There are some works about danger of different parasitic bipolar transistor structures [1], [9], [10]. If particle hits the vicinity of the guard ring it overcomes guard ring potential and opens parasitic bipolar transistor, which injects charges directly to the nodes thought to be immune.…”

Section: Resultsmentioning

confidence: 99%

“…To calculate simulated CS distribution it is essential to gather for each LET point the following set of data: number of simulations, number of upsets and area of the device. Equation for simulated CS for each LET and energy point is (1), where N -a number of the conducted simulations, S -area of the device and N ci -number of the detected upsets.…”

Section: Technique Descriptionmentioning

confidence: 99%

“…In sub -100 technologies, single particle can hit multiple devices simultaneously, producing multiple SETs and multiple SEUs. The effects of multiple SETs are hard to predict, there are some works about more than 10 simultaneous upsets in sub-100 nm memory units [1], [2]. There are some tools that help designers of the space electronics to develop mitigation techniques.…”

Section: Introductionmentioning

confidence: 99%

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Layout-aware Soft Error Rate Estimation Technique for Integrated Circuits under the Environment with Energetic Charged Particles

Balbekov¹,

Gorbunov

Bobkov

2017

J. Phys.: Conf. Ser.

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Abstract. Single Event Transient (SET) is a current and voltage disturbance in an integrated circuit (IC), caused by charged particle impact. In modern IC technologies single charged particle can cause multiple SETs on multiple electrical nodes, this can lead to faults. There are several mitigation techniques with their drawbacks affecting circuit performance. This work presents a comparison of experimental data with simulation results acquired by the means of our technique and tools. Our technique is able to simulate sub-100 nm IC performance under multiple SET using industry standard SPICE simulator, without incorporation of a T-CAD or physical measurements, and taking into account layout of the device.

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Section: Resultsmentioning

confidence: 99%

Section: Technique Descriptionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Layout-aware Soft Error Rate Estimation Technique for Integrated Circuits under the Environment with Energetic Charged Particles

Balbekov¹,

Gorbunov

Bobkov

2017

J. Phys.: Conf. Ser.

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“…In recent years, the study has intensely focused on the influence of temperature on SEE in semiconductor devices. [13][14][15][16][17][18][19][20] Moreover, many researches have shown that temperature has a strong influence on SEEs. For example, Farjallah et al evaluated the variation of Q crit with temperature for 65-nm, 45-nm, 32-nm, and 22-nm bulk silicon CMOS technologies in a temperature range from −50 • C to 150 • C. The SPICE simulation results indicated that Q crit decreases significantly as temperature increases for 6T-SRAM and DICE units, the calculated Q crit changes 88.4% and 99.9% respectively.…”

Section: Introductionmentioning

confidence: 99%

Effect of temperature on heavy ion-induced single event transient on 16-nm FinFET inverter chains

Li¹,

Chi²,

Yan³

et al. 2023

Chinese Phys. B

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In this work, the variation of single event transient (SET) pulse width for high-LET heavy ion irradiation in 16 nm bulk silicon Fin Field-Effect Transistor (FinFET) inverter chains with different driven strengths have been measured at different temperatures. Three-dimensional technology computer-aided design simulations are carried out to study the variation of SET pulse width and saturation current with temperature. Experimental and simulation results indicated that the increase in temperature would enhance the parasitic bipolar effect of bulk FinFET technology, resulting in the increase of SET pulse width. On the other hand, the increase in inverter driven strength will change the layout topology, which has a complex impact on the SET temperature effects of FinFET inverter chains. The experimental and simulation results show that the device with the strongest driven strength has the least dependence on temperature.

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“…Environmental temperature also plays an important role. For instance, [5] showed that MCU sensitivity increases at elevated temperatures. Operating voltage also affects the sensitivity of modern devices, since the critical charge needed to trigger a SEE decreases at low VDD [6], [7].…”

Section: Introductionmentioning

confidence: 99%