This paper presents an experimental study on the sensitivity of a Commercial-Off-The-Shelf (COTS) bulk 65-nm SRAM under 15.6 MeV proton irradiation when powered up at ultra-low bias voltage. Tests were run on stand-by and while reading the memory. Results show obvious evidence indicating that decreasing the bias voltage below 1 V exponentially increases the number of observed errors. SBUs and MCUs (mostly with vertical shapes according to the manufacturers' layout) are reported and their behavior is analyzed in this paper. Predictions on the SEU sensitivity obtained with the MUSCA-SEP3 modeling tool are also provided, and compared with the experimental results. These are also compared with 14.2 MeV neutrons, showing a significant difference in the cross-sections for both irradiation sources. TID tests and GEANT4 simulations were also run to check for the reason behind the difference in the cross-section between these two particles.

In harsh radiation environments, it is well known that the angle of incidence of impinging particles against the surface of the operating devices has significant effects on their sensitivity. This paper discusses the sensitivity underestimations that are made if particle isotropy is not taken into account, by means of an analytical study made with a single event upset predictive platform. To achieve this goal, experimental results carried out with a COTS bulk 130-nm non-volatile SRAM for various incident angles on 14.2 MeV neutrons are firstly discussed. Then, a modeling tool called MUSCA-SEP3 is used to predict the sensitivity of this memory under the same environmental conditions. Predictions and experimental results will be cross-checked, therefore the feasibility of this tool will be demonstrated for testing any other incident angle. Finally, an isotropic environment and an XY SRAM array will be emulated with MUSCA in order to demonstrate that the asymmetrical cross-sections that were observed experimentally for various incidence angles are due to the underlying asymmetry of the metalization/passivation layers within the device with respect to its active silicon. Conclusions will finally be drawn as for the importance of taking into account particle isotropy in radiationground tests.

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This paper presents an analysis of the multiple events (and more specifically, Multiple Cell Upsets or MCUs) that may occur at successive generations of bulk CMOS SRAMs operating under harsh conditions, such as in avionics or space. Such MCU distribution is greatly impacted by the bitcell topology, which, in the International Technology Roadmap for Semiconductors (ITRS) / International Roadmap for Devices and Systems (IRDS) history, experienced a drastic change in the transition between the 90-nm and the 65-nm nodes. Experimental results obtained from proton and neutron accelerators, along with predictions issued from the MUSCA-SEP3 modeling tool, are provided. Various COTS Static Random Access Memories (SRAMs) manufactured by Infineon in bulk CMOS 130-nm nodes down to the 65-nm one were used as targets for the experimental results. Finally, MUSCA-SEP3 was also used to analyze and discuss scaling trends on more modern nodes (45-nm down to 14-nm).

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