Layout-aware Soft Error Rate Estimation Technique for Integrated Circuits under the Environment with Energetic Charged Particles

Abstract

Abstract. Single Event Transient (SET) is a current and voltage disturbance in an integrated circuit (IC), caused by charged particle impact. In modern IC technologies single charged particle can cause multiple SETs on multiple electrical nodes, this can lead to faults. There are several mitigation techniques with their drawbacks affecting circuit performance. This work presents a comparison of experimental data with simulation results acquired by the means of our technique and tools. Our technique is able to simulate sub-100 nm IC performance under multiple SET using industry standard SPICE simulator, without incorporation of a T-CAD or physical measurements, and taking into account layout of the device.