Aging-Temperature-and-Propagation Induced Pulse-Broadening Aware Soft Error Rate Estimation for nano-Scale CMOS

Yan, Aibin; Ling, Yafei; Yang, Kang; Chen, Zhili; Yi, Maoxiang

doi:10.1109/ats.2018.00027

Cited by 3 publications

(2 citation statements)

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“…Similarly, step-4 indicates a valid-convolution ( v ) [19] between S SH (t − T 0 ) in step-3 and propagated SETs in step-2, where convolution product is only given for points at which the signals overlap completely. The valid-convolution results in the generation of two impulse functions δ(t − (T 2 + t Dset )) in blue and δ(t − T 0 )in black with amplitudes A(δ)=0 and A(δ)=1 respectively, where A(δ)=1 represents the non-masked fault as given in (7). The case of A(δ) < 1 represents the masked fault and various cases of step-4 are presented in Fig.…”

Section: E Modeling Of Aging Impact On Set Fault Propagationmentioning

confidence: 99%

“…A. Gebregiorgis in [6] has presented a cross-layer reliability analysis in the presence of soft-errors, aging, and process variation effects. Similarly, the work [7] provides ramification of aging and temperature on Propagation Induced Pulse Broadening (PIPB) effect of Single Event Transient (SET) pulse for nano-scale CMOS. In [8], F. L. Kastensmidt shows that aging and voltage scaling enhance the Soft Error Rate (SER) susceptibility of SRAMbased FPGAs by two times.…”

Section: Introductionmentioning

confidence: 99%

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Modeling Soft-Error Reliability Under Variability

Balakrishnan

Medeiros

Gürsoy

et al. 2021

2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT)

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The Soft-Error (SE) reliability and the effects of Negative Bias Temperature Instability (NBTI) in deep submicron technologies are characterized as the major critical issues of highperformance integrated circuits. The previous scientific research studies provide a comprehensive description that the soft-error vulnerability becomes more severe as the circuit performance degrades with aging. The main reason is the reduction of cell-level critical charge in an aging environment. However, such increased soft-error generation does not necessarily contribute towards circuits' critical functional failures. The proposal of this paper is the experimental investigation of soft error propagation at the aged gate-level by considering the different derating factors like Electrical Derating (EDR), Temporal Derating (TDR), Logical Derating (LDR), and Functional Derating (FDR). As contrary to the previous studies, the results of this work prove that SEU fault propagation probability is reducing in critical paths as time advances while the propagation probability of SET faults is neither reducing nor increasing, but the spot of generation of failure enhancing SETs is shifting within the clock period.

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Section: E Modeling Of Aging Impact On Set Fault Propagationmentioning

confidence: 99%