TEM2P2EST: A Thermal Enabled Multi-model Power/Performance ESTimator

Dhodapkar, Ashutosh S.; Lim, Chee How; Cai, George; Daasch, W.R.

doi:10.1007/3-540-44572-2_9

Cited by 44 publications

(47 citation statements)

References 17 publications

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“…Existing work [1,2,3] considers superscalar architecture. There is hardly any architectural level power simulator for Very Long Instruction Word(VLIW) architecture.…”

Section: Cycle-accurate Vliw Power Simulationmentioning

confidence: 99%

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Power Modeling and Reduction of VLIW Processors

Liao

2003

Compilers and Operating Systems for Low Power

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In this paper, we first present a cycle-accurate power simulator based on the IMPACT toolset. This simulator allows the designer to evaluate both VLIW compiler and microarchitecture innovations for power reduction. Using this simulator, we then develop and compare the following techniques with a bounded performance loss of 1% compared to the case without any dynamic throttling: (i) clock ramping with hardware-based prescan (CRHP), and (ii) clock ramping with compiler-based prediction (CRCP). Experiments using SPEC2000 floating point benchmarks show that the power consumed by floating point units can be reduced by up to 31% and 37%, in CRHP and CRCP respectively.

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“…Existing work [1,2,3] considers superscalar architecture. There is hardly any architectural level power simulator for Very Long Instruction Word(VLIW) architecture.…”

Section: Cycle-accurate Vliw Power Simulationmentioning

confidence: 99%

“…EST [3] have been developed, and used extensively to validate power-efficient microarchitecture innovations including clock gating [4], dynamically reconfiguring resources [5], etc. However, all aforementioned work focuses on the superscalar architecture.…”

Section: Introductionmentioning

confidence: 99%

Power Modeling and Reduction of VLIW Processors

Liao

2003

Compilers and Operating Systems for Low Power

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“…Furthermore, clock gating in [9] is assumed to reduced 100% dynamic power and therefore too ideal. An earlier work [10] proposes chip-level thermal calculation similar to the universal mode in [9]. However, [10] does not consider temperature dependence for leakage power either.…”

Section: Prior Related Workmentioning

confidence: 99%

“…to (10), the heat loss to ambient can be modeled as Po = (T − Ta)/Rt. The unbalance between total power consumption P and heat loss to ambient Po leads to the transient temperature T characterized by (11):…”

Section: Temperature Calculationmentioning

confidence: 99%

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Modeling of coplanar waveguide for buffered clock tree

Chen¹,

He²

ASP-DAC 2004: Asia and South Pacific Design Automation Conference 2004 (IEEE Cat. No.04EX753)

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Power is rapidly becoming the primary design constrain for systems ranging from server computers to handhelds. In this paper we study microarchitecture-level power modeling and management with temperature and voltage scaling. We develop an accurate temperature-dependent leakage power model and efficient temperature calculation, and show that leakage energy and total energy can be different by up to 10X and 30% for temperatures between 35 o C and 110 o C, respectively. Given the growing significance of leakage power and its sensitive dependence on temperature, no power modeling at microarchitecture is accurate without considering dynamic temperature calculation. Furthermore, we discuss a new thermal runaway phenomenon induced by the temperature dependent leakage power and show that in the near future thermal runaway could be a severe problem. We also study the microarchitecture level coupled power and thermal management by clock gating and novel active cooling techniques. We show that with thermal constraints, clock gating can increase maximum system clock by up to 1.5X and reduce leakage energy by up to 68.5% compared to the cases without clock gating, and active cooling techniques providing smaller thermal resistance can further increase the maximum clock by a factor of 2.44X.

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