Technology scaling and reliability: Challenges and opportunities

Huard, V.; Cacho, F.; Federspiel, X.; Arfaoui, W.; Saliva, M.; Angot, D.

doi:10.1109/iedm.2015.7409743

Cited by 16 publications

(7 citation statements)

References 1 publication

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“…Aggressive device scaling has increased the relevance of stress-induced MOSFET degradation (due to dielectric aging mechanisms as Hot Carrier Injection, HCI, and Bias Temperature Instability, BTI) on circuit performance [1]. However, experimental observations of the device degradation under circuit operation conditions together with its impact on the circuit performance are not easy to obtain, because of the difficulty to access the transistor terminals once they are embedded in a more complex circuit.…”

mentioning

confidence: 99%

MOSFET degradation dependence on input signal power in a RF power amplifier

Crespo-Yepes

Barajas

Martín-Martínez

et al. 2017

Microelectronic Engineering

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Aging produced by both DC and RF stress is experimentally analyzed on a RF CMOS power amplifier. The selected circuit topology allows observing individual NMOS and PMOS transistors degradations, as well as the aging effect on the circuit functionality. A direct relation between DC and RF (gain) parameters has been observed. NMOS degradation (both in mobility and V th ) is stronger than that of the PMOS, which identifies the NMOS as the main cause of the RF degradation in this circuit.

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confidence: 99%

MOSFET degradation dependence on input signal power in a RF power amplifier

Crespo-Yepes

Barajas

Martín-Martínez

et al. 2017

Microelectronic Engineering

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“…As for hot-carrier degradation (HCD), which has been repeatedly declared to be the most detrimental reliability concern in ultra-scaled FETs [ 13 , 14 ], although HC induced variability was a subject of experimental [ 15 , 16 , 17 , 18 , 19 , 20 , 21 ] and modeling [ 22 , 23 , 24 , 25 , 26 , 27 , 28 ] studies, to the best of our knowledge there is a limited number of publications devoted to correlation between time-0 and HC stress induced transistor parameter distributions [ 29 , 30 , 31 ], and no simulation studies of this correlation have been performed so far. Schlünder et al [ 29 ] reported a strong correlation between parameters in the

and

tuples (here t is the stress time, while

is the drain current).…”

Section: Introductionmentioning

confidence: 99%

Correlated Time-0 and Hot-Carrier Stress Induced FinFET Parameter Variabilities: Modeling Approach

et al. 2020

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We identify correlation between the drain currents in pristine n-channel FinFET transistors and changes in time-0 currents induced by hot-carrier stress. To achieve this goal, we employ our statistical simulation model for hot-carrier degradation (HCD), which considers the effect of random dopants (RDs) on HCD. For this analysis we generate a set of 200 device instantiations where each of them has its own unique configuration of RDs. For all “samples” in this ensemble we calculate time-0 currents (i.e., currents in undamaged FinFETs) and then degradation characteristics such as changes in the linear drain current and device lifetimes. The robust correlation analysis allows us to identify correlation between transistor lifetimes and drain currents in unstressed devices, which implies that FinFETs with initially higher currents degrade faster, i.e., have more prominent linear drain current changes and shorter lifetimes. Another important result is that although at stress conditions the distribution of drain currents becomes wider with stress time, in the operating regime drain current variability diminishes. Finally, we show that if random traps are also taken into account, all the obtained trends remain the same.

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“…Characterization and modelling Interacted HCA-PBTI Degradation (IHPD) have become a crucially challenging task in industry [7]. Previous research [8][9][10][11] predicted device lifetime at operation Vdd of HCA (Fig.1) or PBTI ( Fig.2) separately, based on the accelerated-voltage method (HCA under Vg=Vd and PBTI under Vg are used in this paper), where unique power-law time and voltage exponents can be observed, respectively. However, this is not the case if PBTI stress is followed by HCA, or HCA stress is followed by PBTI (Fig.3a&4a), where the degradation does not follow a unique power law.…”

Section: Introductionmentioning

confidence: 99%

Interaction between hot carrier aging and PBTI degradation in nMOSFETs: Characterization, modelling and lifetime prediction

Duan

Zhang

et al. 2017

2017 IEEE International Reliability Physics Symposium (IRPS)

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Modelling of the interaction between Hot Carrier Aging (HCA) and Positive Bias Temperature Instability (PBTI) has been considered as one of the main challenges in nanoscale CMOS circuit design. Previous works were mainly based on separate HCA and PBTI instead of Interacted HCA-PBTI Degradation (IHPD). The key advance of this work is to develop a methodology that enables accurate modelling of IHPD through understanding the charging/discharging and generation kinetics of different types of defects during the interaction between HCA and PBTI. It is found that degradation during alternating HCA and PBTI stress cannot be modelled by independent HCI/PBTI. Different stress sequence, i.e. HCA-PBTI-HCA and PBTI-HCA-PBTI, lead to completely different degradation kinetics. Based on the Cyclic Anti-neutralization Model (CAM), for the first time, IHPD has been accurately modelled for both short and long channel devices. Complex degradation mechanisms and kinetics can be well explained by our model. Our results show that device lifetime can be underestimated by one decade without considering interaction.

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Technology scaling and reliability: Challenges and opportunities

Cited by 16 publications

References 1 publication

MOSFET degradation dependence on input signal power in a RF power amplifier

MOSFET degradation dependence on input signal power in a RF power amplifier

Correlated Time-0 and Hot-Carrier Stress Induced FinFET Parameter Variabilities: Modeling Approach

Interaction between hot carrier aging and PBTI degradation in nMOSFETs: Characterization, modelling and lifetime prediction

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