Technological and design constraints for multilevel flash memories

Calligaro, Cristiano; Manstretta, A.; Modelli, Alberto; Torelli, G.

doi:10.1109/icecs.1996.584556

Cited by 35 publications

(8 citation statements)

References 3 publications

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“…The standard CHE program operation of a NOR Flash device is carried out via a constant voltage Î Ð applied to the bit-line of the cell, to provide carrier heating at the drain side, and a ramped voltage with fixed step amplitude Î × and duration × applied to the CG [9]. Fig.…”

Section: Resultsmentioning

confidence: 99%

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Granular electron injection and random telegraph noise impact on the programming accuracy of NOR Flash memories

Compagnoni

Chiavarone²,

Calabrese

et al. 2009

2009 IEEE International Reliability Physics Symposium

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This work investigates for the first time chargegranularity effects during channel hot-electron programming of NOR Flash memories, comparing the granular electron injection and the random telegraph noise limitations to the accuracy of the programming algorithm. The spread of the threshold voltage shift that is determined by the electron injection statistics is studied as a function of the channel hot-electron programming conditions, explaining the results by an analytical model accounting for the sub-poissonian nature of the electron transfer to the floating gate. The scaling trend of the injection statistical spread is then investigated on NOR technologies ranging from ½ ¼ to nm and its contribution to the width of the threshold voltage distribution in presence of a program verify level is separated from that given by random telegraph noise.

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Section: Resultsmentioning

confidence: 99%

“…Referring to the staircase programming algorithm, commonly used to achieved a tight control of the final Î Ì distribution [9], the spread is studied as a function of the 0 10 20 30 40 50 60 70 80 90 100…”

Section: Introductionmentioning

confidence: 99%

Granular electron injection and random telegraph noise impact on the programming accuracy of NOR Flash memories

Compagnoni

Chiavarone²,

Calabrese

et al. 2009

2009 IEEE International Reliability Physics Symposium

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“…Therefore, the programming speed can be lower than the memory programming condition. With a lower programming speed, the V th variation can be reduced [32].…”

Section: E Reliability Discussionmentioning

confidence: 99%

A Novel Convolution Computing Paradigm Based on NOR Flash Array With High Computing Speed and Energy Efficiency

Han

Huang

Xiang

et al. 2019

IEEE Trans. Circuits Syst. I

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Convolution is one of the key operations in signal processing and machine learning applications. In this paper, we propose a novel convolution computing paradigm based on the NOR Flash array (NFA) that is capable of executing the 2-D convolution computing in one clock cycle. In order to demonstrate the feasibility and efficiency of the proposed convolution computing paradigm, the feature extraction task on an image with the size of 20 × 20 is executed using the NFA structure. We also prove the NOR Flash-driven convolution computing is capable of processing the image with a larger size. This paper presents a new approach to realize convolution computing with high speed and energy efficiency for the signal processing and convolution neural network.

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“…Especially flash memory is popular since it is light and portable, and many new techniques are introduced to flash memory to increase the capacity [1]. The multilevel approach for flash memory enables more than 1 bit of information on a single cell [2]. For high density devices, 8,16, and 32 levels can be used for each cell in a multi level cell (MLC) flash memory.…”

Section: Introductionmentioning

confidence: 99%

Interference compensation technique for multilevel flash memory

Jeon

Kim

Shin

et al. 2011

2011 IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS)

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Multilevel cell flash memory devices are galUlUg popularity because it can increase the memory capacity by storing two or more bits to a single cell. However, when the number of levels of a cell increases, the inter-cell interference which shifts cell (threshold) voltage becomes more critical. Thereare two approaches to alleviate the errors caused by the voltage shift.One is the error correcting codes, and the other is the signal processing methods. We focus on signal processing methods to reduce the cell to cell interference which causes the voltage shift, and propose algorithms which reduce the voltage shift effects by cIassfying and compensating erratic cells. The simulation resultsshow that the proposed algorithms are effective for interference reduction.

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Technological and design constraints for multilevel flash memories

Cited by 35 publications

References 3 publications

Granular electron injection and random telegraph noise impact on the programming accuracy of NOR Flash memories

Granular electron injection and random telegraph noise impact on the programming accuracy of NOR Flash memories

A Novel Convolution Computing Paradigm Based on NOR Flash Array With High Computing Speed and Energy Efficiency

Interference compensation technique for multilevel flash memory

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