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1999
DOI: 10.1016/s0924-4247(99)00199-5
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Techniques to improve the flatness of reflective micro-optical arrays

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Cited by 14 publications
(8 citation statements)
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“…The backplane is manufactured at commercial VLSI foundries using standard CMOS methods and processes, which unfortunately are not optimized with optical performance in mind. In consequence, although the resulting devices can be made flat at the pixel level to prevent scattering and improve diffraction efficiency, they have bows and warps at the die level [34], which frequently gives rise to major optical aberrations.…”
Section: Modulator Aberrations and Correctionmentioning
confidence: 99%
“…The backplane is manufactured at commercial VLSI foundries using standard CMOS methods and processes, which unfortunately are not optimized with optical performance in mind. In consequence, although the resulting devices can be made flat at the pixel level to prevent scattering and improve diffraction efficiency, they have bows and warps at the die level [34], which frequently gives rise to major optical aberrations.…”
Section: Modulator Aberrations and Correctionmentioning
confidence: 99%
“…Unfortunately, the silicon backplane manufactured using standard CMOS methods is not flat [20], which frequently gives rise to important optical aberration. Such distortion is too strong to ignore when using SLMs for wavefront control in applications such as laser beam steering, diffractive optical element generation, or emulation of atmospheric turbulence.…”
Section: Introductionmentioning
confidence: 99%
“…Optimisation of the ECR machine has achieved deposition uniformities of 1% over a 75 mm wafer which compares well to commercially available silica spacer particles which may have variations of 10%. However, it should be noted that the thickness of the photoresist and the spacer width affect the spacer height [4] and must be calibrated. 6.…”
Section: Examples Of Cmp Planarisation [4]mentioning
confidence: 99%
“…6. Backplane flattening and device assembly [4] When the wafer is diced the bow on individual chips can become quite severe (up to l.5um)). One of the prime causes of silica spacers fracturing and ploughing into soft aluminium is that during cell assembly the optically flat cover glass is pressed down on the device.…”
Section: Examples Of Cmp Planarisation [4]mentioning
confidence: 99%