&lt;title&gt;Review of the history and technology of micromachined miniature displays using foundry-produced silicon backplanes&lt;/title&gt;

Walton, A.J.; Vass, D.G.; Underwood, Ian; Bodammer, G.; Calton, David; Seunarine, K.; Stevenson, J.T.M.; Gundlach, A.M.

doi:10.1117/12.364442

Cited by 6 publications

(3 citation statements)

References 5 publications

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“…The lateral dimensions of the silicon chip are of the order of 15 mm square. Typical pixel pitches vary from 10 µm to 40 µm [3]. The basic structure of the display engine is shown in figure 1 where it is evident, that the display works in reflection.…”

Section: Figure 1 Display Enginementioning

confidence: 99%

“…In reaction to these stresses, the die warps or bows after dicing with the degree of warp depending on the exact manufacturing process. To illustrate this we have measured the bow of three die for four different microdisplay backplanes described in [3], and then removed the circuitry by wet etching (10 minutes aluminium etch, 30 minutes HF, 10 minutes aluminium etch, 2 minutes silicon etch). The die warp was then measured again.…”

Section: Origin Of Die Scale Warpmentioning

confidence: 99%

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Microdisplay Packaging Challenge

Bodammer

Calton²,

Miremont³

et al. 2000

30th European Solid-State Device Research Conference

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The packaging of ferro-electric liquid crystal over silicon (FLCOS) microdisplays presents itself as a formidable challenge to the package designer. The overall assembly should be lightweight, rugged, and incorporate the display engine, the illumination unit and the viewing optics. Good optical performance of the displays depends on many variables that need to be optimised. The silicon chip acts as part of an optical device and so standard packaging procedures are not readily applicable. In particular, the silicon chip requires significant post-processing to ensure it is both smooth and flat even after assembly. Selection of a suitable packaging strategy is key to success. In this paper we evaluate various methods of first level packaging of the silicon display engine.

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Section: Figure 1 Display Enginementioning

confidence: 99%

Section: Origin Of Die Scale Warpmentioning

confidence: 99%

Microdisplay Packaging Challenge

Bodammer

Calton²,

Miremont³

et al. 2000

30th European Solid-State Device Research Conference

View full text Add to dashboard Cite

show abstract

“…For that reason the CMOS backplane has to be smooth and flat. Chemical mechanical polishing, self-aligned insulator filled trench and damascene technology (see [8] and references therein for a full description of the various process) can provide surfaces with sub-nm RMS surface roughness. However, local planarization does not overcome global chip bow.…”

Section: Introductionmentioning

confidence: 99%