Tailoring Multilevel‐Stable Remanence States in Exchange‐Biased System through Spin‐Orbit Torque

Yun, Jijun; Bai, Qiaoning; Yan, Ze; Chang, Meixia; Mao, Jian; Zuo, Yalu; Yang, Dezheng; Xi, Li; Xue, Desheng

doi:10.1002/adfm.201909092

Cited by 57 publications

(45 citation statements)

References 49 publications

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“…[ 18 ] Meanwhile, the nonvolatility of these 2 n magnetization configurations in a single cell could serve as a pivotal ingredient for realizing multifunction and reconfigurable logics‐in‐memory. [ 31–38 ] Such a versatile platform could thus be useful for in‐memory computing architecture for potentially breaking the von Neumann bottleneck and reducing energy cost and computation delay due to data shuffling. [ 5,39,40 ] These important facts motivate the present study.…”

Section: Introductionmentioning

confidence: 99%

Electrically Reconfigurable 3D Spin‐Orbitronics

Dong

Zhou

et al. 2020

Adv Funct Materials

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The explosive demands of storage capacity and the von Neumann bottleneck of modern computer architectures trigger many innovations in information technology. Amongst them, nonvolatile spintronics attract considerable attentions for which can embed the computation capability into memory, enable neuromorphic, and probabilistic computing. These exciting progresses typically rely on the manipulation of the relative magnetization orientations of two magnetic layers. By extending to 3D spintronic architectures made of multiple magnetic layers (n), the exponentially increased 2n magnetic states can provide ample opportunities for implementing novel spintronic functionalities. Here, through building perpendicularly magnetized 3D spin‐orbitronic architectures – [Pt/Fe1−xTbx/Si3N4]n multilayers, it is demonstrated the electrical programing of 2n memory states via current‐induced spin–orbit torques (SOTs), and the accompanied reconfigurable multifunction in‐memory logic features in a single four‐terminal Hall device. Further, an electrical readout of these 2n states, together with the implementation of Boolean logic gates and digital circuitry such as 2–4 and 3–8 decoders, are successfully conducted. More complex logic circuits are also envisioned. The experiments thus substantiate 3D spin‐orbitronic structures as a promising platform for exponentially boosting the storage capacity and accommodating in‐memory computing that can be important for promoting the emerging 3D nanospintronics.

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Section: Introductionmentioning

confidence: 99%

Electrically Reconfigurable 3D Spin‐Orbitronics

Dong

Zhou

et al. 2020

Adv Funct Materials

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“…[2] Beyond today's binary storage, a new proposal is to use the multi-level cell (MLC) to store more than two bits. [5][6][7][8] In addition, the MLCs can also be employed in spin-neuron-like devices, which have a large potential to significantly increase their computational performances. [9,10] Recent studies reported different efforts toward the multi-level devices, such as spinorbit torque based devices, [5] antiferromagnetic-based devices, [6] resistive random access memories (ReRAMs), [7] and ferroelectric field-effect transistors (FeFET).…”

Section: Introductionmentioning

confidence: 99%

“…[5][6][7][8] In addition, the MLCs can also be employed in spin-neuron-like devices, which have a large potential to significantly increase their computational performances. [9,10] Recent studies reported different efforts toward the multi-level devices, such as spinorbit torque based devices, [5] antiferromagnetic-based devices, [6] resistive random access memories (ReRAMs), [7] and ferroelectric field-effect transistors (FeFET). [8] However, a successful design transferable to the industrial processes has not been One of the critical issues in spintronics-based technologies is to increase the data storage density.…”

Section: Introductionmentioning

confidence: 99%

Multi‐Level Switching and Reversible Current Driven Domain‐Wall Motion in Single CoFeB/MgO/CoFeB‐Based Perpendicular Magnetic Tunnel Junctions

Fidalgo

Silva

et al. 2020

Adv Elect Materials

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One of the critical issues in spintronics‐based technologies is to increase the data storage density. Current strategy is based on shrinking the devices size down to tens of nanometers, or several nanometers, which is reaching its limit. A new proposal is to use multi‐level cells (MLCs) to store more than two bits in each cell. In this work, the multi‐level switching is realized in CoFeB/MgO/CoFeB based nano‐scale single perpendicular magnetic tunnel junctions (p‐MTJs) with three or four stable resistance states. A large range of writing currents for each state is obtained, accompanying with a good repeatability of set‐reset operations between different states. The developed multi‐domain model perfectly matches the experimental results, reflecting the magnetic behaviors during multi‐level switching. Furthermore, current‐driven domain wall (DW) motion is revealed in the circular p‐MTJs, where the DW position can be reversibly manipulated by applied current. To design high‐performance multi‐level p‐MTJs, the parameter diagrams are calculated, suggesting various feasible strategies to improve the multi‐level switching through materials optimization and devices geometry. In summary, the demonstration of multi‐level switching in single p‐MTJ shows the high potential of realizing the new generation of p‐MTJ‐based multi‐level spintronic devices, such as multi‐level memories and spin‐neuron devices.

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“…In addition to the STT effect, the magnetization reorientation can be also induced by spin‐orbit torque (SOT). As shown in Figure 1c, [ 41 ] the SOT effect in a multilayer of heavy metal (HM), FM, and antiferromagnetic (AFM), which may consist of various other magnetic combinations, originates from a spin‐orbit interaction, such as the spin Hall effect (SHE). [ 75 ] When an in‐plane current flows through the HM layer with a collinear magnetic field, the electrons with antiparallel spins experience spin‐scattering to its interface while going through this layer, leading to spin accumulation at the interface.…”

Section: Memristors and Cbasmentioning

confidence: 99%

Memristive Devices for New Computing Paradigms

Kim

Jang

2020

Advanced Intelligent Systems

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Since the first programmable computers were invented, people have no longer been restricted to paper or canvas to process and store information. Due to the significant advances in complementary metal-oxide-semiconductor (CMOS) technology, computing performance has increased drastically based on Moore's law [1] and Dennard's law. [2] Currently, computing systems are designed based on von Neumann architecture systems, in which the processor and memory regions are separated and bridged by data buses. With the introduction of cache and improved storage capabilities, and with the development of transistor technology, computing performance has improved significantly. However, the processor and memory performance have improved at different rates. Consequently, the performance gap observed between memory hierarchies causes a delay that is known as a von Neumann bottleneck. According to the 2018 International Roadmap for Devices and Systems (IRDS), conventional computing architectures are expected to reach their physical limits in terms of performance by 2024. [3] However, three significant problems arise, of which the first is volatility. A CMOS operates by reading the capacitance values, which is advantageous in distinguishing on and off states. However, small technical nodes result in high capacity leaks, energy losses, and reliability issues. The second obstacle involves scaling. Because CMOS-based von Neumann computing systems have been developed using a three-terminal structure, which consists of a source, drain, and gate, the device size typically exceeds 6F 2 even with smaller feature sizes. As a result, it has become a common trend to fabricate smaller and more integrated devices. The third problem involves speed and energy issues. The incorporation of more sensors and edge computing products has led to data explosion; therefore, data are processed slower due to von Neumann bottlenecks, and an enormous amount of energy is required. Although features, such as bit-cost scalable (BiCS) technology [4] and a merger of processor and memory have been introduced to overcome these issues, [5] it is still necessary to transition to novel computing systems that are more advanced than CMOS-based von Neumann architectures. Memristor (memory resistor) technology, which was proposed by Chua, [6] has gained prominence as the most promising novel computing candidate. Unlike a CMOS, memristors, which show pinched I-V hysteresis, identify values through the resistive reading method rather than through the capacitance reading method. [7] Therefore, new computing systems based on memristors would give the opportunity to step toward next computing technologies. Moreover, because memristors can be integrated into crossbar arrays (CBAs), the theoretical density is 4F 2 , which is expected to overcome the scaling limit of CMOS-based computing. In this article, we introduce four types of memristor materials and present their operation mechanisms in detail. We describe what memristive CBAs consist of and how they operate, and we demonstrat...

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Tailoring Multilevel‐Stable Remanence States in Exchange‐Biased System through Spin‐Orbit Torque

Cited by 57 publications

References 49 publications

Electrically Reconfigurable 3D Spin‐Orbitronics

Electrically Reconfigurable 3D Spin‐Orbitronics

Multi‐Level Switching and Reversible Current Driven Domain‐Wall Motion in Single CoFeB/MgO/CoFeB‐Based Perpendicular Magnetic Tunnel Junctions

Memristive Devices for New Computing Paradigms

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