Since the first programmable computers were invented, people have no longer been restricted to paper or canvas to process and store information. Due to the significant advances in complementary metal-oxide-semiconductor (CMOS) technology, computing performance has increased drastically based on Moore's law [1] and Dennard's law. [2] Currently, computing systems are designed based on von Neumann architecture systems, in which the processor and memory regions are separated and bridged by data buses. With the introduction of cache and improved storage capabilities, and with the development of transistor technology, computing performance has improved significantly. However, the processor and memory performance have improved at different rates. Consequently, the performance gap observed between memory hierarchies causes a delay that is known as a von Neumann bottleneck. According to the 2018 International Roadmap for Devices and Systems (IRDS), conventional computing architectures are expected to reach their physical limits in terms of performance by 2024. [3] However, three significant problems arise, of which the first is volatility. A CMOS operates by reading the capacitance values, which is advantageous in distinguishing on and off states. However, small technical nodes result in high capacity leaks, energy losses, and reliability issues. The second obstacle involves scaling. Because CMOS-based von Neumann computing systems have been developed using a three-terminal structure, which consists of a source, drain, and gate, the device size typically exceeds 6F 2 even with smaller feature sizes. As a result, it has become a common trend to fabricate smaller and more integrated devices. The third problem involves speed and energy issues. The incorporation of more sensors and edge computing products has led to data explosion; therefore, data are processed slower due to von Neumann bottlenecks, and an enormous amount of energy is required. Although features, such as bit-cost scalable (BiCS) technology [4] and a merger of processor and memory have been introduced to overcome these issues, [5] it is still necessary to transition to novel computing systems that are more advanced than CMOS-based von Neumann architectures. Memristor (memory resistor) technology, which was proposed by Chua, [6] has gained prominence as the most promising novel computing candidate. Unlike a CMOS, memristors, which show pinched I-V hysteresis, identify values through the resistive reading method rather than through the capacitance reading method. [7] Therefore, new computing systems based on memristors would give the opportunity to step toward next computing technologies. Moreover, because memristors can be integrated into crossbar arrays (CBAs), the theoretical density is 4F 2 , which is expected to overcome the scaling limit of CMOS-based computing. In this article, we introduce four types of memristor materials and present their operation mechanisms in detail. We describe what memristive CBAs consist of and how they operate, and we demonstrat...

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In resistive switching memories or artificial synaptic devices, halide perovskites have attracted attention for their unusual features such as rapid ion migration, adjustable composition, and facile synthesis. Herein, the environmentally friendly and highly air stable CsCu 2 I 3 perovskite films are used as the active layer in the Au/CsCu 2 I 3 /ITO/glass artificial synapses. The device shows variable synaptic plasticities such as long-term and short-term synaptic plasticity, paired-pulse facilitation, and spike-timing-dependent plasticity by combining potentiation and depression along the formation of conductive filaments. The performances of the devices are maintained for 160 days under ambient conditions. Additionally, the accuracy evaluation of the CsCu 2 I 3 -based artificial synapses performs exceptionally well with the MNIST and Fashion MNIST data sets, demonstrating high learning accuracy in deep neural networks. Using the novel B-site engineered halide perovskite material with extreme air stability, this study paves the way for artificial synaptic devices for nextgeneration in-memory hardware.

Organometallic and all‐inorganic halide perovskites (HPs) have recently emerged as promising candidate materials for resistive switching (RS) nonvolatile memory due to their current–voltage hysteresis caused by fast ion migration. Lead‐free and all‐inorganic HPs have been researched for non‐toxic and environmentally friendly RS memory devices. However, only HP‐based devices with electrochemically active top electrode (TE) exhibit ultra‐low operating voltages and high on/off ratio RS properties. The active TE easily reacts to halide ions in HP films, and the devices have a low device durability. Herein, RS memory devices based on an air‐stable lead‐free all‐inorganic dual‐phase HP (AgBi2I7‐Cs3Bi2I9) are successfully fabricated with inert metal electrodes. The devices with Au TE show filamentary RS behavior by conducting‐bridge involving Ag cations in HPs with ultra‐low operating voltages (<0.15 V), high on/off ratio (>107), multilevel data storage, and long retention times (>5 × 104 s). The use of a closed‐loop pulse switching method improves reversible RS properties up to 103 cycles with high on/off ratio above 106. With an extremely small bending radius of 1 mm, the devices are operable with reasonable RS characteristics. This work provides a promising material strategy for lead‐free all‐inorganic HP‐based nonvolatile memory devices for practical applications.

Recently, artificial synapses involving an electrochemical reaction of Li-ion have been attributed to have remarkable synaptic properties. Three-terminal synaptic transistors utilizing Li-ion intercalation exhibits reliable synaptic characteristics by exploiting the advantage of non-distributed weight updates owing to stable ion migrations. However, the three-terminal configurations with large and complex structures impede the crossbar array implementation required for hardware neuromorphic systems. Meanwhile, achieving adequate synaptic performances through effective Li-ion intercalation in vertical two-terminal synaptic devices for array integration remains challenging. Here, two-terminal Au/LixCoO2/Pt artificial synapses are proposed with the potential for practical implementation of hardware neural networks. The Au/LixCoO2/Pt devices demonstrated extraordinary neuromorphic behaviors based on a progressive dearth of Li in LixCoO2 films. The intercalation and deintercalation of Li-ion inside the films are precisely controlled over the weight control spike, resulting in improved weight control functionality. Various types of synaptic plasticity were imitated and assessed in terms of key factors such as nonlinearity, symmetricity, and dynamic range. Notably, the LixCoO2-based neuromorphic system outperformed three-terminal synaptic transistors in simulations of convolutional neural networks and multilayer perceptrons due to the high linearity and low programming error. These impressive performances suggest the vertical two-terminal Au/LixCoO2/Pt artificial synapses as promising candidates for hardware neural networks