Memristive Devices for New Computing Paradigms

Abstract

Since the first programmable computers were invented, people have no longer been restricted to paper or canvas to process and store information. Due to the significant advances in complementary metal-oxide-semiconductor (CMOS) technology, computing performance has increased drastically based on Moore's law [1] and Dennard's law. [2] Currently, computing systems are designed based on von Neumann architecture systems, in which the processor and memory regions are separated and bridged by data buses. With the introduction of cache and improved storage capabilities, and with the development of transistor technology, computing performance has improved significantly. However, the processor and memory performance have improved at different rates. Consequently, the performance gap observed between memory hierarchies causes a delay that is known as a von Neumann bottleneck. According to the 2018 International Roadmap for Devices and Systems (IRDS), conventional computing architectures are expected to reach their physical limits in terms of performance by 2024. [3] However, three significant problems arise, of which the first is volatility. A CMOS operates by reading the capacitance values, which is advantageous in distinguishing on and off states. However, small technical nodes result in high capacity leaks, energy losses, and reliability issues. The second obstacle involves scaling. Because CMOS-based von Neumann computing systems have been developed using a three-terminal structure, which consists of a source, drain, and gate, the device size typically exceeds 6F 2 even with smaller feature sizes. As a result, it has become a common trend to fabricate smaller and more integrated devices. The third problem involves speed and energy issues. The incorporation of more sensors and edge computing products has led to data explosion; therefore, data are processed slower due to von Neumann bottlenecks, and an enormous amount of energy is required. Although features, such as bit-cost scalable (BiCS) technology [4] and a merger of processor and memory have been introduced to overcome these issues, [5] it is still necessary to transition to novel computing systems that are more advanced than CMOS-based von Neumann architectures. Memristor (memory resistor) technology, which was proposed by Chua, [6] has gained prominence as the most promising novel computing candidate. Unlike a CMOS, memristors, which show pinched I-V hysteresis, identify values through the resistive reading method rather than through the capacitance reading method. [7] Therefore, new computing systems based on memristors would give the opportunity to step toward next computing technologies. Moreover, because memristors can be integrated into crossbar arrays (CBAs), the theoretical density is 4F 2 , which is expected to overcome the scaling limit of CMOS-based computing. In this article, we introduce four types of memristor materials and present their operation mechanisms in detail. We describe what memristive CBAs consist of and how they operate, and we demonstrat...

Impact of Electrolyte Incorporation in Anodized Niobium on Its Resistive Switching

“…Volatility, scaling, speed and energy issues are the main obstacles in the field of complementary metal-oxide-semiconductor (CMOS) technology [ 1 ]. With advantages that include compatibility with CMOS and resistive instead of capacitive reading, memristors are frontrunners in the new generation of resistive random-access memory (RRAM) technology.…”

“…The study was motivated by the previous reports investigating the effect of tuning electrochemical parameters on anodic oxide growth [ 20 , 21 , 22 , 23 ] or memristive behavior, confirming the influence of electrolyte selection as the most relevant [ 24 , 25 ]. Since unipolar devices can be used for dense integration on diode selectors and bipolar ones show higher device lifetime [ 14 ], the controllable switching of the Nb anodic oxide memristors may be beneficial regarding the range of their possible applications [ 1 , 26 , 27 , 28 , 29 ]. Finally, the switching mechanism based on CF formation, influenced by their size and positioning, is suggested for devices showing reversible switching in unipolar and bipolar mode based on TEM investigation.…”

Halide perovskite for low‐power consumption neuromorphic devices

“…Based on its low cost, low temperature processability, low ion mobility activity and the formation of reversible p‐i‐n structures, ion‐conducting OHP is very suitable for memristors and synaptic devices. To date, OHP based memristors have been investigated and many papers have been reported 42–45 . In recent years, many research teams have also discovered that the conduction behavior is electronic mixed with ionic transport.…”

A Marr's Three‐Level Analytical Framework for Neuromorphic Electronic Systems

“…In the last two sections, we have already seen examples of how advanced technologies enable electronic mimics of individual parts of the neural system with demonstrated simple computational functionalities. We do not intend to survey the neuromorphic hardware implementation again as this has been done in numerous reviews, just to name a few, at materials level, [ 48,661–722 ] at device level, [ 10,244,263,723–790 ] at more circuit level, or above. [ …”