System Level Tools for DSP in FPGAs

Hwang, J.C.M.; Milne, Brent; Shirazi, N.; Stroomer, Jeffrey

doi:10.1007/3-540-44687-7_55

Cited by 47 publications

(33 citation statements)

References 6 publications

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“…System Generator for DSP is a software platform, integrated within M\ATLAB and Simulink [8] tools from The MathWorks, that allows for the design of DSP systems using The Xilinx BlockSet [9,10]. System Generator also handles the automatic generation of peripherals for MicroBlaze [11], synthesizable on Xilinx FPGAs.…”

Section: Design and Implementation Methodologymentioning

confidence: 99%

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Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements

Viejo

Bellido

Millan

et al. 2006

2006 International Symposium on Industrial Embedded Systems

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This contribution successfully accomplished the design and implementation of an advanced DSP circuit for direct measurements of electrical network parameters (RMS and real and reactive power) with application to network monitoring and quality assurance.The device is implemented on a mid-range Xilinx Spartan-3 family FPGA and includes an OPB interface so that it can be integrated as a standardperipheral ofa microprocessor system like the MicroBlaze. Special attention has been paid to resources optimization and accuracy with simulated error below l%.

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Section: Design and Implementation Methodologymentioning

confidence: 99%

“…First, FIR filter design and coefficient calculation have been carried out using FDATool, a MATLAB package [10]. FDATool features an advanced interface that allows the design to define filter type, filter order, pass and stop frequencies, passband ripple, stopband attenuation, etc.…”

Section: System Design and Implementationmentioning

confidence: 99%

Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements

Viejo

Bellido

Millan

et al. 2006

2006 International Symposium on Industrial Embedded Systems

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“…The focus of this work is on the DSP domain, and as a consequence, the benchmarks used to test the architectures in this study have been developed in Xilinx's System Generator for MATLAB [23]. Figure 2 shows the design flow and how our tool interacts with existing software.…”

Section: Design Flow and Problem Formulationmentioning

confidence: 99%

“…Similarly, the number of binary variables representing the floorplan of the underlying architecture δ qrx (18)(19)(20)(21) is n regions (n regions − 1), where n regions is the number of regions. Finally, the number of binary variables representing the floorplanning of nodes onto the architecture δ uir (22)(23)(24) is at most 2n nodes n regions . A consequence of this is that, while valuable lower-bounds can be achieved, the computation required for exact solution explodes even for benchmarks and architecture templates of modest size.…”

Section: Heuristic Determination Of Reconfigurable Architecturesmentioning

confidence: 99%

“…The benchmarks include: an LMS adaptive filter, as used in [31]; a multi-channel IIR filter and a Costas Loop, as supplied with Xilinx System Generator [23]; a programmable two dimensional 5x5 image convolution on a raster-scanned image, based on that supplied with System Generator; an ADPCM encoder [32]; and a Horner scheme polynomial evaluator. All benchmarks are of a similar hardware complexity when implemented in their time-optimal strategy, area figures relative to the size of a slice are given in Table II. The first results presented evaluate the efficiency of the floorplanning and technology mapping heuristic for the different types of benchmark, in a similar fashion to Section V-A.…”

Section: B Architectural Explorationmentioning

confidence: 99%

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Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices

Smith

Constantinides

Cheung

2008

IEEE Trans. VLSI Syst.

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Abstract-This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, we investigate the appropriate mix and floorplan of heterogeneous elements: multipliers, RAMs, and LUT-based logic, in order to maximise the performance of a set of DSP benchmark applications, given a fixed silicon budget. A mathematical programming framework is introduced, along with a set of heuristics, capable of providing upper-bounds on the achievable reconfigurable-to-fixed-logic performance ratio. Moreover, we use linear-programming bounding procedures from the operations research community to provide lower-bounds on the same quantity. Our results provide, for the first time, quantifications of the optimal performance/area-enhancing capability of multipliers and RAM blocks within a system context. The approach detailed provides a formal mechanism to explore future technology nodes.

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References

2011

Design for Embedded Image Processing on FPGAs

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System Level Tools for DSP in FPGAs

Cited by 47 publications

References 6 publications

Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements

Efficient Design and Implementation on FPGA of a MicroBlaze Peripheral for Processing Direct Electrical Networks Measurements

Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices

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