Integrated Floorplanning, Module-Selection, and Architecture Generation for Reconfigurable Devices

Abstract

Abstract-This paper is concerned with the application of formal optimisation methods to the design of mixed-granularity FPGAs. In particular, we investigate the appropriate mix and floorplan of heterogeneous elements: multipliers, RAMs, and LUT-based logic, in order to maximise the performance of a set of DSP benchmark applications, given a fixed silicon budget. A mathematical programming framework is introduced, along with a set of heuristics, capable of providing upper-bounds on the achievable reconfigurable-to-fixed-logic performance ratio. Moreover, we use linear-programming bounding procedures from the operations research community to provide lower-bounds on the same quantity. Our results provide, for the first time, quantifications of the optimal performance/area-enhancing capability of multipliers and RAM blocks within a system context. The approach detailed provides a formal mechanism to explore future technology nodes.

AutoReloc: Automated Design Flow for Bitstream Relocation on Xilinx FPGAs

“…Several algorithms have already been proposed for traditional reconfigurable designs, such as in [8], [10], [11], [12], [13], [14], [15]. However, these algorithms usually outputs very compact static part, i.e.…”

Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods

“…In comparison with such approaches, analytical tools offer the ability to explore a much wider design space within any given computational time budget. The analytical tool of [Smith et al 2008], for instance, has been used in the past to produce optimal architectures within the accuracy of the formulation. However, the model suffers from its exponential time complexity with respect to the number of circuit blocks.…”

“…The need for estimation and optimization techniques has therefore become crucial to divide, conquer and explore the large design space of potential architectures. While there exists a significant amount of work on homogeneous architecture design [Emmert and Bhatia 1999], [Hutton 2006], there is currently limited research on heterogeneous FPGA architectures consisting of a mix of coarse and fine grain components [Feng and Mehta 2006], [Smith et al 2008].…”

“…An ILP model has been used in our previous work to achieve optimal solutions to problems such as architecture generation [Smith et al 2008]. The model allows the elimination of the dependencies on heuristic algorithms and provides more efficient ways to explore the design space.…”

Area estimation and optimisation of FPGA routing fabrics

“…Recently, a number of research publications have appeared that advocate the use of some form of analytical model to determine FPGA architecture parameters [1,2,3,4,5]. The main contribution of [2,3,4] has been to demonstrate that equation-based high-level models can relatively accurately capture some of the design trade-offs present in FPGA architectures, without resorting to computationally intensive empirical methods based on tools such as VPR [6].…”