System-level power analysis methodology applied to the AMBA AHB bus [SoC applications]

Caldari, M.; Conti, Massimo; Coppola, M.; Crippa, Paolo; Orcioni, Simone; Pieralisi, Lorenzo; Turchetti, Claudio

doi:10.1109/date.2003.1253801

Cited by 32 publications

(25 citation statements)

References 6 publications

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“…In order to increase the bus capacity and provide more flexibility in resource allocation, the multi-layer bus architecture (ARM, 2004) and a multi-channel Network-on-Chip (NoC) (Sanghun Lee and Lee, 2004) architecture have been proposed. However, for those techniques, the drawback is that increasing the number of bus layers or channels would imply an increase in the overhead of the cost or area, the power consumption and the complexity of SoC systems design (AHB, 2001;ARM, 2004;Caldari et al, 2003). For example, the gate count would grow exponentially in the multi-layer bus architecture, when the number of bus layers and the number of PE's have been increased (AHB, 2001).…”

Section: Introductionmentioning

confidence: 99%

Multi-layer bus minimization for SoC

Chen

Tsai

2010

Journal of Systems and Software

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Section: Introductionmentioning

confidence: 99%

Multi-layer bus minimization for SoC

Chen

Tsai

2010

Journal of Systems and Software

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“…For delay computations, we use our gate delay model [17] described in Section III-A below. Current literature on bus modeling such as [25], [24], [23] are focused at RTL or higher level (i.e., transaction level) whereas we propose physicallevel models to estimate delay, power, and area. Our models can be plugged into any high-level synthesis tool or network simulator to aid in estimation of metrics.…”

Section: Logic Modelingmentioning

confidence: 99%

On modeling and sensitivity of via count in SOC physical implementation

Jeong

Kahng

Yao

2008

2008 International SoC Design Conference

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Abstract-Multiprocessor systems-on-chip (MPSoCs) are emerging as a popular SoC design platform. However, major challenges arise from nonscaling global wire delay and from the reuse of intellectual properties (IPs) from different vendors to meet tight time-to-market constraints. Designing the appropriate communication fabrics for such heterogeneous systems becomes a challenging task. In this paper, we present accurate delay, power, and area models for bus-based and packetswitched communication architectures. We also integrate our models into the COSI-OCC [30] predicts that future generations of high-end IC designs will operate in the 10-20 GHz range, with multi-Gbit/s communication between cores. A major challenge designers face is to provide a reliable and functional interconnection between the components of the design [1].As device sizes shrink to keep up with Moore's Law, major challenges arise from non-scalable global wire delays. Recently, designers have moved from a computation-centric view of chip design to a communication-centric view, largely due to the increasing significance of interconnect delay versus gate delay in current and future technologies. Based on the premise that interconnection technology will be a limiting factor for achieving SoC operational goals, we propose a characterization framework for the two most dominant interconnection architectures in today's designs: (1) busbased architecture (i.e., shared medium) and (2) packet-switched architecture (i.e., as employed in current NoC designs). We review each of these architectures and then propose accurate and fast systemlevel models for performance, power, and area to aid fast and efficient design space exploration. For bus-based designs, we develop models for AMBA (Advanced Microcontroller Bus Architecture) [29], a popular on-chip bus for ARM processors. For NoC-based designs, we integrate our proposed models into the COSI-OCC communication synthesis tool [19] and show they substantially change the NoC outcome of system-level design exploration. Because state-of-the-art communication architectures are quite complex, with multiple components, there has been little research on modeling and early-designstage prediction. In this context, we have developed an integrated communication modeling library that:• models popular low-and high-level communication structures, • predicts delay, power, and area at early design stage with as much accuracy as feasible, • is usable by system-level designer, and • allows technology extrapolation. In this invited paper, we have integrated content from our previous works [16], [17], [18]. Section II describes the current state-of-theart bus-based communication architectures and proposes accurate delay, power, and area models for such architectures. Section III describes network-on-chip communication architectures and presents our modeling approach through two examples of physical link and router power modeling. Section IV shows the impact of increased accuracy of our models on system-level design choices and...

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“…In contrast, the work presented in this paper considers the case where functional transaction-level models for the cores already exist, and generates power models for those existing transactions. Integration of power models for certain components of the AMBA AHB bus into a transaction-level modeling framework was explored in [13]. In [14], a function based power estimation method was presented for embedded software executing on microprocessors.…”

Section: Power Estimation Using Transaction-level Modelingmentioning

confidence: 99%

Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems

Dhanwada

Bergamaschi

Dungan

et al. 2005

Des Autom Embed Syst

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Transaction-Level models have emerged as an efficient way of modeling systemson-chip, with acceptable simulation speed and modeling accuracy. Nevertheless, the high complexity of current architectures and bus protocols make it very challenging to develop and verify such models. This paper presents the transaction-level models developed at IBM for PowerPC and CoreConnect-based systems. These models can be simulated in a SystemC environment for functional verification and power estimation. Detailed transactionbased power models were developed. Comparisons between the simulated models and real hardware resulted in errors below 15% in timing accuracy, and below 11% in power estimation compared against gate-level power. These results demonstrate the efficiency of our transaction-level models for early analysis and design space exploration.

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System-level power analysis methodology applied to the AMBA AHB bus [SoC applications]

Cited by 32 publications

References 6 publications

Multi-layer bus minimization for SoC

Multi-layer bus minimization for SoC

On modeling and sensitivity of via count in SOC physical implementation

Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems

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