Multi-layer bus minimization for SoC

Chen, Ya-Shu; Tsai, Hsin-Liang; Lo, Shi-Wu

doi:10.1016/j.jss.2009.07.041

Cited by 1 publication

(1 citation statement)

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“…The trade-off issue has become even more critical with the growing number of bus layers because more layers will lead to increased overheads, such as a larger gate count, more power consumption, and greater design complexity [5]. Note that the overheads are not mainly from the bus layers themselves but the gate count (which remains a major factor in the price of a chip) required by processors to implement the interconnections [2], [7].…”

Section: Introductionmentioning

confidence: 99%

Multilayer Bus Optimization for Real-Time Embedded Systems

Hsiu¹,

Hsieh²,

Lee³

et al. 2012

IEEE Trans. Comput.

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A major challenge in the design of multicore embedded systems is how to tackle the communications among tasks with performance requirements and precedence constraints. In this paper, we consider the problem of scheduling real-time tasks over multilayer bus systems with the objective of minimizing the communication cost. We show that the problem is N P-hard and determine the best possible approximation ratio of approximation algorithms. First, we propose a polynomial-time optimal algorithm for a restricted case where one multilayer bus, and the unit execution time and communication time are considered. The result is then extended as a pseudopolynomial-time optimal algorithm to consider multiple multilayer buses with arbitrary execution and communication times, as well as different timing constraints and objective functions. We compare the performance of the proposed algorithm with that of some popular heuristics, and provide further insights into the multilayer bus system design.

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Section: Introductionmentioning

confidence: 99%