Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems

Dhanwada, Nagu; Bergamaschi, Reinaldo A.; Dungan, William W.; Nair, Indira; Gramann, Paul J.; Dougherty, William E.; Lin, Iuon-Chang

doi:10.1007/s10617-006-9586-7

Cited by 16 publications

(7 citation statements)

References 9 publications

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“…Dhanwada et al (Narayanan et al, 2005;Dhanwada et al, 2005) proposed a generic flow for power estimation at the SystemC level ( Figure 4). The output of circuit simulation is a multi-level tree (called HTLP tree), where the granularity of the transaction gradually increases as we move towards the root, from power consumption values for primitive transactions, to a complex sequence of actions.…”

Section: Api Based Approachesmentioning

confidence: 99%

Processor power estimation techniques: a survey

Sultan¹,

Ananthanarayanan²,

Sarangi³

2014

IJHPSA

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Since the end of the nineties, power dissipation has been regarded as a first order design constraint in processors. Increased power dissipation along with the resultant rise in die temperature is considered as the single largest bottleneck for increasing processor frequency and complexity. Consequently, it is very important from both a technical as well as commercial perspective to accurately estimate processor power such that designers can tailor their architecture, software and systems to minimize power consumption. In this paper, we provide a survey of most of the processor specific power estimation techniques proposed after the mid nineties. In specific, we look at estimating power both at design time as well as runtime. The former approach is more suitable for early stage architectural exploration, and the latter approach is more germane to creating power efficient application software. We broadly focus on estimating power using system level models, architectural simulation, hardware performance counters, on-chip temperature profiles, and program execution profiles. We showcase a broad range of methods for power estimation using simulators, compilers, profilers, and sophisticated mathematical analysis routines.

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Section: Api Based Approachesmentioning

confidence: 99%

Processor power estimation techniques: a survey

Sultan¹,

Ananthanarayanan²,

Sarangi³

2014

IJHPSA

View full text Add to dashboard Cite

show abstract

“…Using this approach for recent processors and systems is not realistic. Dhawada et al [5] proposed a power estimation methodology for a monoprocessor PowerPC and CoreConnect-based system at the TLM level. Their power modeling methodology is based on a fine-grain activity characterization at the gate level, which needs a huge amount of development time.…”

Section: Related Workmentioning

confidence: 99%

An efficient power estimation methodology for complex RISC processor-based platforms

Rethinagiri

Atitallah²,

Dekeyser

et al. 2012

Proceedings of the Great Lakes Symposium on VLSI

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In this contribution, we propose an efficient power estimation methodology for complex RISC processor-based platforms. In this methodology, the Functional Level Power Analysis (FLPA) is used to set up generic power models for the different parts of the system. Then, a simulation framework based on virtual platform is developed to evaluate accurately the activities used in the related power models. The combination of the two parts above leads to a heterogeneous power estimation that gives a better trade-off between accuracy and speed. The usefulness and effectiveness of our proposed methodology is validated through ARM9 and ARM CortexA8 processor designed respectively around the OMAP5912 and OMAP3530 boards. This efficiency and the accuracy of our proposed methodology is evaluated by using a variety of basic programs to complete media benchmarks. Estimated power values are compared to real board measurements for the both ARM940T and ARM CortexA8 architectures. Our obtained power estimation results provide less than 3% of error for ARM940T processor, 3.5% for ARM CortexA8 processor-based system and 1x faster compared to the state-of-the-art power estimation tools.

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“…Using this approach for recent processors and systems is not realistic. Dhawada et al [5] proposed a power estimation methodology for a monoprocessor PowerPC and CoreConnect-based system at the TLM level. Their power modeling methodology is based on a fine-gsrain activity characterization at the gate level, which needs a huge amount of development time.…”

Section: Related Workmentioning

confidence: 99%

A system level power consumption estimation for MPSoC

Rethinagiri¹,

Atitallah²,

Dekeyser³

2011

2011 International Symposium on System on Chip (SoC)

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This paper proposes an efficient Hybrid System Level (HSL) power estimation methodology for MPSoC. Within this methodology, the Functional Level Power Analysis (FLPA) is extended to set up generic power models for the different parts of the system. Then, a simulation framework is developed at the transactional level to evaluate accurately the activities used in the related power models. The combination of the above two parts lead to a hybrid power estimation that gives a better trade-off between accuracy and speed. The proposed methodology has several benefits: it considers the power consumption of the embedded system in its entirety and leads to accurate estimates without a costly and complex material. The proposed methodology is also scalable for exploring complex embedded architectures. The usefulness and effectiveness of our HSL methodology is validated through a typical mono-processor and multiprocessor embedded system designed around the Xilinx Virtex II Pro FPGA board.

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Transaction-level modeling for architectural and power analysis of PowerPC and CoreConnect-based systems

Cited by 16 publications

References 9 publications

Processor power estimation techniques: a survey

Processor power estimation techniques: a survey

An efficient power estimation methodology for complex RISC processor-based platforms

A system level power consumption estimation for MPSoC

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