A system level power consumption estimation for MPSoC

Rethinagiri, Santhosh Kumar; Atitallah, Rabıe Ben; Dekeyser, Jean-Luc

doi:10.1109/issoc.2011.6089692

Cited by 15 publications

(9 citation statements)

References 12 publications

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“…This tool simplifies application porting as well as enables the user to choose the processor architecture upon which to perform hardware/software co-simulation. PETS was initially developed for the evaluation of MPSoC systems [7][8][9]. In ParaDIME, we have extended it to model a variety of other systems, including GPUs [10], DSPs, FPGAs [11] and multi-core (dual-and quad-core) ARM processors [12].…”

Section: Heterogeneous Computingmentioning

confidence: 99%

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers

Rethinagiri

Palomar

Sobe

et al. 2015

Microprocessors and Microsystems

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a b s t r a c tDramatic environmental and economic impact of the ever increasing power and energy consumption of modern computing devices in data centers is now a critical challenge. On the one hand, designers use technology scaling as one of the methods to face the phenomenon called dark silicon (only segments of a chip function concurrently due to power restrictions). On the other hand, designers use extreme-scale systems such as teradevices to meet the performance needs of their applications which in turn increases the power consumption of the platform. In order to overcome these challenges, we need novel computing paradigms that address energy efficiency. One of the promising solutions is to incorporate parallel distributed methodologies at different abstraction levels.The FP7 project ParaDIME focuses on this objective to provide different distributed methodologies (software-hardware techniques) at different abstraction levels to attack the power-wall problem. In particular, the ParaDIME framework will utilize: circuit and architecture operation below safe voltage limits for drastic energy savings, specialized energy-aware computing accelerators, heterogeneous computing, energy-aware runtime, approximate computing and power-aware message passing. The major outcome of the project will be a noval processor architecture for a heterogeneous distributed system that utilizes future device characteristics, runtime and programming model for drastic energy savings of data centers. Wherever possible, ParaDIME will adopt multidisciplinary techniques, such as hardware support for message passing, runtime energy optimization utilizing new hardware energy performance counters, use of accelerators for error recovery from sub-safe voltage operation, and approximate computing through annotated code. Furthermore, we will establish and investigate the theoretical limits of energy savings at the device, circuit, architecture, runtime and programming model levels of the computing stack, as well as quantify the actual energy savings achieved by the ParaDIME approach for the complete computing stack with the real environment.

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Section: Heterogeneous Computingmentioning

confidence: 99%

ParaDIME: Parallel Distributed Infrastructure for Minimization of Energy for data centers

Rethinagiri

Palomar

Sobe

et al. 2015

Microprocessors and Microsystems

Self Cite

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“…Following the idea of FLPA, the work in [16] and [20] uses functional models for different types of components found in ESL platforms to deliver the input for power models. Those power models track the internal state of the component and output the estimated power consumption accordingly.…”

Section: Related Workmentioning

confidence: 99%

Improving ESL power models using switching activity information from timed functional models

Schürmans

Zhang

Leupers

et al. 2014

Proceedings of the 17th International Workshop on Software and Compilers for Embedded Systems

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Early design space exploration at Electronic System Level (ESL) can be done either using untimed functional models, timed functional models or performance models, which use random or zero data instead of the actual data. In order to be applicable to the two latter types, ESL power estimation approaches often rely only on sub-block activity information. This work shows the benefit of additionally using the switching activity information of actual data available in timed functional models for power estimation. A case study shows that a considerable gain in accuracy can be achieved while causing only a moderate simulation slowdown.

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“…This tool simplifies application porting as well as enables the user to choose the processor architecture upon which to perform hardware/software co-simulation. PETS was initially developed for the evaluation of MPSoC systems [10], [9], [11]. In ParaDIME, we have extended it to model a variety of other systems, including DSPs, FPGAs and multi-core (dual-and quad-core) ARM processors [13], [12], [15].…”

Section: ) Heterogeneous Computingmentioning

confidence: 99%