On modeling and sensitivity of via count in SOC physical implementation

Abstract

Abstract-Multiprocessor systems-on-chip (MPSoCs) are emerging as a popular SoC design platform. However, major challenges arise from nonscaling global wire delay and from the reuse of intellectual properties (IPs) from different vendors to meet tight time-to-market constraints. Designing the appropriate communication fabrics for such heterogeneous systems becomes a challenging task. In this paper, we present accurate delay, power, and area models for bus-based and packetswitched communication architectures. We also integrate our models into the COSI-OCC [30] predicts that future generations of high-end IC designs will operate in the 10-20 GHz range, with multi-Gbit/s communication between cores. A major challenge designers face is to provide a reliable and functional interconnection between the components of the design [1].As device sizes shrink to keep up with Moore's Law, major challenges arise from non-scalable global wire delays. Recently, designers have moved from a computation-centric view of chip design to a communication-centric view, largely due to the increasing significance of interconnect delay versus gate delay in current and future technologies. Based on the premise that interconnection technology will be a limiting factor for achieving SoC operational goals, we propose a characterization framework for the two most dominant interconnection architectures in today's designs: (1) busbased architecture (i.e., shared medium) and (2) packet-switched architecture (i.e., as employed in current NoC designs). We review each of these architectures and then propose accurate and fast systemlevel models for performance, power, and area to aid fast and efficient design space exploration. For bus-based designs, we develop models for AMBA (Advanced Microcontroller Bus Architecture) [29], a popular on-chip bus for ARM processors. For NoC-based designs, we integrate our proposed models into the COSI-OCC communication synthesis tool [19] and show they substantially change the NoC outcome of system-level design exploration. Because state-of-the-art communication architectures are quite complex, with multiple components, there has been little research on modeling and early-designstage prediction. In this context, we have developed an integrated communication modeling library that:• models popular low-and high-level communication structures, • predicts delay, power, and area at early design stage with as much accuracy as feasible, • is usable by system-level designer, and • allows technology extrapolation. In this invited paper, we have integrated content from our previous works [16], [17], [18]. Section II describes the current state-of-theart bus-based communication architectures and proposes accurate delay, power, and area models for such architectures. Section III describes network-on-chip communication architectures and presents our modeling approach through two examples of physical link and router power modeling. Section IV shows the impact of increased accuracy of our models on system-level design choices and...

A power-constrained MPU roadmap for the International Technology Roadmap for Semiconductors (ITRS)

“…Hence, total number of m-point nets in the entire system can be described by Equation (5). Subsequently, replacing m with F o+1, where F o is fanout, gives Equation (6).…”

“…Hence, wirelength estimation has always been instrumental in determining physically achievable design implementations [4]. Likewise, interconnect fanout can be used in interconnect modeling to enable more accurate delay and power calculations.Based on different design stages and available information at each stage, we categorize wirelength estimation approaches into: (1) analytical, (2) netlist-based, and (3) placement-based [1], [6]. Analytical methods are based on Rent's rule, a famous wellestablished empirical relationship, and assume that the netlist is not known.…”

“…Based on different design stages and available information at each stage, we categorize wirelength estimation approaches into: (1) analytical, (2) netlist-based, and (3) placement-based [1], [6]. Analytical methods are based on Rent's rule, a famous wellestablished empirical relationship, and assume that the netlist is not known.…”