8th International Symposium on Quality Electronic Design (ISQED'07) 2007
DOI: 10.1109/isqed.2007.154
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System Level Estimation of Interconnect Length in the Presence of IP Blocks

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Cited by 3 publications
(2 citation statements)
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“…Their work, however, lacks from considering the complexity of the circuits into account and hence the average wirelength obtained form these techniques overestimate the actual wirelength for circuits with large chip area. We have proposed a methodology to estimate the average wirelength in [1,2,4,6], which is based on a hierarchical placement of the circuit into a square Manhattan grid in the presence of blockages. This methodology is very similar to Donath's method for estimating total wirelength.…”
Section: Wirelength Estimation In Presence Of Ip Blocksmentioning
confidence: 99%
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“…Their work, however, lacks from considering the complexity of the circuits into account and hence the average wirelength obtained form these techniques overestimate the actual wirelength for circuits with large chip area. We have proposed a methodology to estimate the average wirelength in [1,2,4,6], which is based on a hierarchical placement of the circuit into a square Manhattan grid in the presence of blockages. This methodology is very similar to Donath's method for estimating total wirelength.…”
Section: Wirelength Estimation In Presence Of Ip Blocksmentioning
confidence: 99%
“…The probabilistic analysis to extract transparent-block and detour parts of interconnect length for horizontally, vertically and diagonally adjacent sub-circuits have been done in [1] completely and so is omitted here for brevity. For the probability distribution of wires, the assumption of uniform probability distribution for standard cells from [2,6,10] seems to be inaccurate since it does not consider the optimal placement tools behavior to place connected cells closer to each other.…”
Section: Wirelength Estimation In Presence Of Ip Blocksmentioning
confidence: 99%