Topological constraints for E. F. Rent's work on microminiature packaging and circuitry

Vernizzi, Graziano; Lanzerotti, Mary; Kujawski, J.; Weatherwax, A. T.

doi:10.1147/jrd.2014.2307225

Cited by 1 publication

(3 citation statements)

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“…The computer elements in a gate-level circuit (terminals; gates; nets; fanout) can be mapped to the elements in an integrated circuit designs (terminal vertices; gate vertices; edges; net vertices, respectively) [18]. In this mapping, each circuit is mapped to a mathematical graph with one boundary; each gate is mapped to a gate-vertex; each edge is mapped to a net; a net with fanout greater than or equal to two is mapped to a net-vertex; and each pin (input pin, output pin, or input-output pin) is mapped to a terminal-vertex.…”

Section: Circuitsmentioning

confidence: 99%

“…Terminal vertices are located on the circuit boundary. Two terminal vertices are connected with an edge; a net-vertex and a gate vertex are also connected with an edge [18]. The number of blocks is equal to the sum of the number of gate vertices and the number of net vertices.…”

Section: Circuitsmentioning

confidence: 99%

“…The Euler characteristic χ for a circuit with vertex count V , edge count E, and face count F is given by the expression [18],…”

Section: Circuitsmentioning

confidence: 99%

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Topological constraints of gate-level circuits obtained through standard cell recognition (SCR)

Hsia

Vernizzi

Lanzerotti

et al. 2015

2015 National Aerospace and Electronics Conference (NAECON)

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This paper presents topological constraints of gate-level circuits obtained through standard cell recognition applied to gate-level commercial microelectronics verification. A suite of topological constraints, including the gate vertex count, net vertex count, terminal count, blocks, circuit genus, Euler characteristic, and number of faces are extracted from gate-level circuits obtained through standard cell recognition. Topological constraints are computed for two full adder cells at fourth level of abstraction and for two full adder cells at the third level of abstraction. Two mathematical frameworks are also introduced to describe physically distinct situations in hardware that are represented in a schematic as functionally equivalent. The first method uses the concept of a braid word, and the second method uses the concept of a crossing vertex. Schematic braid words corresponding to each of two full adder cell schematics at fourth level of abstraction and for two full adder cell schematics at the third level of abstraction are derived. Chip braid words corresponding to the set of unique physical designs that could potentially be realized in chip hardware from a schematic are obtained and discussed. Potential capabilities of these approaches for gate-level circuits are discussed.

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Section: Circuitsmentioning

confidence: 99%

Section: Circuitsmentioning

confidence: 99%