Tutorial on congestion prediction

Taghavi, Taraneh; Dabiri, Foad; Nahapetian, Ani; Sarrafzadeh, Majid

doi:10.1145/1231956.1231961

Cited by 8 publications

(3 citation statements)

References 67 publications

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“…However, an MSS design with optimized PPA must be easily routable in the physical design stage and therefore a noncongested design is preferred [11]. Lesser congestion improves throughput and reduces power dissipation in interconnects by reducing the wire length [12]. Hence, we consider routing congestion as the fourth optimization objective.…”

Section: ) Congestionmentioning

confidence: 99%

Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems

Narang

Fell

Gupta

et al. 2015

2015 28th IEEE International System-on-Chip Conference (SOCC)

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Embedded memories are the key contributor to the chip area, dynamic power dissipation and also form a significant part of critical path for high performance advanced SoCs. Therefore, optimal selection of memory instances becomes imperative for SoC designers. While EDA tools have evolved over the past years to optimally select standard logic cells depending on the timing and the power constraints, optimal memory selection is largely a manual process. We propose a framework to optimize power, performance, and area (PPA) of a memory subsystem (MSS) by including floorplan dependent delays and power consumption in interconnects and glue logic of the MSS in the pre-RTL stage. Through this framework, we demonstrate that for a 4 Mb assembly of SRAM instances, dynamic power is reduced by 44%, area by 49%, and leakage by 71% with the floorplan aware selection. The framework has the capability to use different estimates, when routing congestion is important (for example, in low cost processes with less number of metal layers). We also show that the interconnect delays are reduced by about 68% and dynamic power by 58%, if additional metal layers are available for routing compared to a low cost 6 metal process.

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Section: ) Congestionmentioning

confidence: 99%

Floorplan and congestion aware framework for optimal SRAM selection for memory subsystems

Narang

Fell

Gupta

et al. 2015

2015 28th IEEE International System-on-Chip Conference (SOCC)

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“…These estimated lengths can be used to choose among several competing placement solutions [14]. In [21][22][23], several examples of a-posteriori net length estimation techniques are proposed.…”

Section: Net Length Estimation Typesmentioning

confidence: 99%

“…Several net length estimation techniques are proposed to provide insight about net length during or before physical design [1,2,[6][7][8][12][13][14][15][16][17][18][19][20][21][22][23][24]. This insight helps the designer to improve the quality of placement and routing of a circuit.…”

Section: Introductionmentioning

confidence: 99%

A pre-placement individual net length estimation model and an application for modern circuits

et al. 2011

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A-priori individual interconnect length estimates can be used to make placement efficient and reduce delay and power consumption in a circuit. However, finding lengths of individual interconnects before their terminals have been placed can be a daunting task. In this thesis, the main characteristics that need to be considered while designing an individual a-priori length estimation technique for today's integrated circuits are discussed. Then, a technique for estimating individual interconnect lengths for mixed-size circuits based on Radial Basis Functions (RBFs) is proposed. The advantage of using RBFs, is that the given data do not need to be fitted into a pre-defined model such as a polynomial. In this thesis, a method is proposed to calculate a suitable variance parameter of the RBFs. An application of the length estimator is proposed where a predictor-corrector framework for clustering that can be used to improve the results of placement is implemented.

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