Evaluation, prediction and reduction of routing congestion

Saeedi, Mehdi; Zamani, Morteza Saheb; Jahanian, Ali

doi:10.1016/j.mejo.2007.07.122

Cited by 8 publications

(2 citation statements)

References 37 publications

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“…The authors in [9] introduced a new routing congestion analysis tool called CGRIP that operates on a flexible model of global routing and models the congestion estimation using Integer Linear Programming. Statistical and probabilistic model-based routing congestion estimation tools are discussed in [10]. Among the other works that employ non-machine learning-based models in order to estimate routing congestion, [11,12] are some of the significant ones.…”

Section: Related Literaturementioning

confidence: 99%

Congestion Prediction in FPGA Using Regression Based Learning Methods

Goswami

Bhatia

2021

Electronics

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Design closure in general VLSI physical design flows and FPGA physical design flows is an important and time-consuming problem. Routing itself can consume as much as 70% of the total design time. Accurate congestion estimation during the early stages of the design flow can help alleviate last-minute routing-related surprises. This paper has described a methodology for a post-placement, machine learning-based routing congestion prediction model for FPGAs. Routing congestion is modeled as a regression problem. We have described the methods for generating training data, feature extractions, training, regression models, validation, and deployment approaches. We have tested our prediction model by using ISPD 2016 FPGA benchmarks. Our prediction method reports a very accurate localized congestion value in each channel around a configurable logic block (CLB). The localized congestion is predicted in both vertical and horizontal directions. We demonstrate the effectiveness of our model on completely unseen designs that are not initially part of the training data set. The generated results show significant improvement in terms of accuracy measured as mean absolute error and prediction time when compared against the latest state-of-the-art works.

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Section: Related Literaturementioning

confidence: 99%

Congestion Prediction in FPGA Using Regression Based Learning Methods

Goswami

Bhatia

2021

Electronics

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“…The most suitable bin to insert each buffer is chosen based on the congestion level of all the overlapping bins. After the congestion of each bin is estimated by using the models presented in [23], each buffer is planned to be inserted inside the least congested bin. A sample of the congestiondriven buffer assignment is shown in Fig.…”

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confidence: 99%