System in Package with Mounted Capacitor for Reduced Parasitic Inductance in Voltage Regulators

Hashimoto, Takayuki; Kawashima, T.; Uno, T.; Satou, Yoshihisa; Matsuura, N.

doi:10.1109/ispsd.2008.4538962

Cited by 8 publications

(3 citation statements)

References 6 publications

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“…This high frequency power loop contains input capacitors, top switch, and bottom switch. The parasitic inductance of this high frequency power loop significantly impacts the switching speed of devices, peak drain to source voltage spike, and the efficiency of converter [15] [16]. Generally, the larger loop parasitics inductance, the higher power loss.…”

Section: Packaging and Layout Parasiticsmentioning

confidence: 99%

High frequency high power density 3D integrated Gallium Nitride based point of load module

Ji¹,

Reusch²,

Lee³

2012

2012 IEEE Energy Conversion Congress and Exposition (ECCE)

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The Gallium Nitride (GaN) transistors offer the capability of high efficiency at high operation frequency. This paper will discuss the characteristics of enhancement mode and depletion mode GaN transistors; the high frequency GaN converter design considerations include gate driving, reducing dead-time loss, minimizing parasitics inductance, and the three dimension (3D) technology to integrate the active layer with low profile low temperature co-fired ceramic (LTCC) magnetic substrate to achieve high power density. The final demonstrations are two 12 V to 1.2 V conversion integrated point of load (POL) modules: a single-phase10A 800W/in 3 5MHz converter, a two-phase 20 A 1000 W/in 3 5 MHz converter using the depletion mode GaN transistors. These converters offer unmatched power density compared to state-of-the-art industry products and research.

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Section: Packaging and Layout Parasiticsmentioning

confidence: 99%

High frequency high power density 3D integrated Gallium Nitride based point of load module

Ji¹,

Reusch²,

Lee³

2012

2012 IEEE Energy Conversion Congress and Exposition (ECCE)

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“…The high frequency loop inductance, L Loop , while not as penalizing to switching speeds as common source inductance, still negatively impacts switching performance [18], [19]. Another major drawback of high frequency loop inductance is the drain-to-source voltage spike induced during the switching transition, shown in figure 4, given by: …”

Section: Introductionmentioning

confidence: 99%

Effectively paralleling gallium nitride transistors for high current and high frequency applications

Reusch¹,

Strydom²

2015

2015 IEEE Applied Power Electronics Conference and Exposition (APEC)

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Gallium nitride (GaN) based power devices are rapidly being adopted due to their ability to operate at frequencies and switching speeds beyond the capability of silicon (Si) power MOSFETs. In this paper, we will discuss paralleling high speed GaN transistors in applications requiring higher output current. This work will discuss the impact of in-circuit parasitics on performance and propose printed circuit board (PCB) layout methods to improve parallel performance of high speed GaN transistors. Four parallel half bridges in an optimized layout operated as a 48 V to 12 V, 480 W, 300 kHz, 40 A single phase buck converter achieving efficiencies above 96.5% from 35% to 100% load will be demonstrated. Also in this paper, we will discuss the latest eGaN ® FET developments including the fourth generation devices designed for higher current handling capability.978-1-4799-6735-3/15/$31.00 ©2015 IEEE

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“…In [18], researchers looked at minimizing voltage spikes across the dc link by using interleaved layout configuration. References [19] and [20] compared the switching loop inductance with respect to the placement of the dc-bus capacitor. Reference [21] proposed an analytical approach for designing dc-bus bar to reduce the total stray inductance.…”

Section: Introductionmentioning

confidence: 99%

Analysis of High-Speed PCB With SiC Devices by Investigating Turn-Off Overvoltage and Interconnection Inductance Influence

Noppakunkajorn

Han

Sarlioglu

2015

IEEE Trans. Transp. Electrific.

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Silicon (Si) carbide (SiC)-based power switching devices provide significant performance improvements compared to conventional Si devices. The superior characteristics enable considerable loss, size, and weight reduction of power converters in the powertrain of hybrid/electric vehicles. However, the fast switching capability of SiC devices renders them more vulnerable to parasitic inductances in the circuit. The purpose of this paper is to analyze the impact of interconnection inductances to overvoltage during turn-OFF transient of SiC devices. To understand the switching behavior of the SiC devices, the ringing and overshoots of the voltage caused by the device capacitance and interconnection inductances are considered. Parametric studies are conducted to compare the influences of printed circuit board (PCB) and packaging inductances on the peak turn-OFF overvoltage under various operating conditions. A prototype half-bridge buck converter with SiC MOSFETs is constructed for the experiments. Experimental results are shown to validate the simulation results. Index Terms-Hybrid/electric vehicle, parasitic inductance, silicon (Si) carbide (SiC), voltage overshoot.

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System in Package with Mounted Capacitor for Reduced Parasitic Inductance in Voltage Regulators

Cited by 8 publications

References 6 publications

High frequency high power density 3D integrated Gallium Nitride based point of load module

High frequency high power density 3D integrated Gallium Nitride based point of load module

Effectively paralleling gallium nitride transistors for high current and high frequency applications

Analysis of High-Speed PCB With SiC Devices by Investigating Turn-Off Overvoltage and Interconnection Inductance Influence

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