System-in-package testing: problems and solutions

Appello, D.; Bernardi, P.; Grosso, M.; Reorda, Matteo Sonza

doi:10.1109/mdt.2006.79

Cited by 31 publications

(6 citation statements)

References 8 publications

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“…SiP test flow involves several steps [2], which is much different from SoC test or PCB test, as shown in fig.1. It requires individual chip-level, chip-to-chip interconnections test, post-packaging test, and final system testing.…”

Section: Sip Test Flowmentioning

confidence: 99%

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Research of parallel scheduling strategy for hierarchical SiP test using IEEE 1500 standard

Zhao

Jiang

Liu

2014

2014 Joint IEEE International Symposium on the Applications of Ferroelectric, International Workshop on Acoustic Transduction M

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A SiP(System in Package) consists of multiple chips stacked and connected within a package. And SiP testing is a significant and growing problem owing to the limited accessibility and its particular test flow. It requires individual chip-level, interconnections test, post-packaging test and final system testing. This paper presents an overview of SiP test flow and the problem encountered by SiP test, and suggests its solution the IEEE 1500 Standard for Embedded Core Test (SECT). IEEE 1500 provides test access structure and mechanisms to implement the parallel scheduling test for hierarchical SiP .

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Section: Sip Test Flowmentioning

confidence: 99%

“…A SiP itself may contain some chips in a hierarchical manner. A test access mechanisms (TAM) only for chips at the top level of a hierarchy is insufficient [2]. An efficient and effective hierarchical test structure is needed to test the chips at the lower level of a hierarchy.…”

Section: Introductionmentioning

confidence: 99%

Research of parallel scheduling strategy for hierarchical SiP test using IEEE 1500 standard

Zhao

Jiang

Liu

2014

2014 Joint IEEE International Symposium on the Applications of Ferroelectric, International Workshop on Acoustic Transduction M

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“…Thus far, no SiP TAP standard exists, but architectures have been proposed based on the IEEE 1149.1 standard [22] or the IEEE 1500 standard [23]. TDI TCK TMS TDO 1 0 die1 TDI TCK TMS TDO TDI TCK TMS TDO die2 TDI TCK TMS TDO TDI TCK TMS TDO die3 1 0 TDO TDI TCK TMS1 TMS2 TMS3 TDO TDI TCK TMS1 TMS2 TMS3 TDI TCK TMS TDO TDI TCK TMS TDO 0 1 0 1 0 TDI TCK TMS TDO die2 TDI TCK TMS TDO TDI TCK TMS TDO TDI TCK TMS TDO die3 TDI TCK TMS TDO TDI TCK TMS …”

Section: Sip Test Access Portmentioning

confidence: 99%

System-in-Package, a Combination of Challenges and Solutions

Cauvet¹,

Bernard

Renovell

2007

12th IEEE European Test Symposium (ETS'07)

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System-in-Package(SiP) has recently become a significant technology in the semiconductor industry, offering to the consumer applications many new product features without increasing the overall form factor. In this talk, the basic SiP concepts are first discussed, showing difference between SiP and SoC, illustrated by some examples, drawn from real-life cases. The specific challenges are considered from the testing point of view, focussing on the assembled yield and defect level for the packaged SiP. Various bare-die test techniques to find known-good-dies are described including their limitations, followed by two techniques to test the SiP at the system level: functional system test and embedded component test. A brief discussion on future SiP design and test challenges concludes the presentation.

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“…The first level of integration is known as the system-on-chip (SoC), which is a deep integration of the system’s components onto a single chip. The second level of integration is known as the SiP, which is a side-by-side or stacking of many chips [ 10 ]. To accomplish particular goals, the packaging is performed in 2D, 2.5D, or 3D.…”

Section: Introductionmentioning

confidence: 99%

A Review of System-in-Package Technologies: Application and Reliability of Advanced Packaging

Wang

Yang

et al. 2023

Micromachines

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The system-in-package (SiP) has gained much interest in the current rapid development of integrated circuits (ICs) due to its advantages of integration, shrinking, and high density. This review examined the SiP as its focus, provides a list of the most-recent SiP innovations based on market needs, and discusses how the SiP is used in various fields. Reliability issues must be resolved if the SiP is to operate normally. Three factors—thermal management, mechanical stress and electrical properties—can be paired with specific examples in order to detect and improve package reliability. This review provides a thorough overview of SiP technology, serves as a guide and foundation for the SiP in package reliability design, and addresses the challenges and potential for further development of this kind of package.

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System-in-package testing: problems and solutions

Cited by 31 publications

References 8 publications

Research of parallel scheduling strategy for hierarchical SiP test using IEEE 1500 standard

Research of parallel scheduling strategy for hierarchical SiP test using IEEE 1500 standard

System-in-Package, a Combination of Challenges and Solutions

A Review of System-in-Package Technologies: Application and Reliability of Advanced Packaging

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