Research of parallel scheduling strategy for hierarchical SiP test using IEEE 1500 standard

Abstract

A SiP(System in Package) consists of multiple chips stacked and connected within a package. And SiP testing is a significant and growing problem owing to the limited accessibility and its particular test flow. It requires individual chip-level, interconnections test, post-packaging test and final system testing. This paper presents an overview of SiP test flow and the problem encountered by SiP test, and suggests its solution the IEEE 1500 Standard for Embedded Core Test (SECT). IEEE 1500 provides test access structure and mechanisms to implement the parallel scheduling test for hierarchical SiP .