Synthesize pass transistor logic gate by using free binary decision diagram

Tachibana, Masayoshi

doi:10.1109/asic.1997.617005

Cited by 5 publications

(1 citation statement)

References 6 publications

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“…For example, the variable s associated with the node in Figure 1(b) is the control signal in the multiplexer in Figure 1(a). Pass‐transistor logic (PTL) has the capability to implement a logic function with a smaller number of transistors and less power dissipation, and several studies on realizing circuits with PTL have been published 1–4, showing that this technology is viable. Unfortunately, a function may require BDD representation of exponential size if it is mapped onto PTL 5.…”

Section: Introductionmentioning

confidence: 99%

BDD‐based synthesis for mixed CMOS/PTL logic

Kao

2011

Circuit Theory & Apps

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SUMMARYPower consumption and performance are two important design constraints for logic synthesis in design automation. In this paper, we propose an efficient synthesis algorithm to minimize power dissipation and optimize performance of the given digital circuits by constructing a binary decision diagram (BDD) whose nodes can be implemented by CMOS logics and pass-transistor logics (PTL) in a cell library.For BDD mapped circuits, the conventional synthesis algorithms need three cells: the CMOS cell, PTL cell, and CMOS remapping pattern. In the proposed synthesis algorithm, we first refine the cell library structure to two kinds of cells: PTL and CMOS cells. Next, a new algorithm is presented to select the suitable cells so that the areas and power dissipation can be decreased when the logic functions of the given digital circuits are mapped into BDD. The efficiency of this algorithm has been shown in the experimental results.

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Section: Introductionmentioning

confidence: 99%

BDD‐based synthesis for mixed CMOS/PTL logic

Kao

2011

Circuit Theory & Apps

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Technology mapping for high-performance static CMOS and pass transistor logic designs

Jiang

Sapatnekar

Bamji³

2001

IEEE Trans. VLSI Syst.

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Two new techniques for mapping circuits are p r oposed in this paper. The rst method, called the odd-level transistor replacement OTR method, has a goal that is similar to that of technology mapping, but without the restriction of a xed library size, and maps a circuit to a virtual library of complex static CMOS gates. The second technique, the Static CMOS PTL method, uses a mix of static CMOS and pass transistor logic PTL to realize the circuit, and utilizes the relation between PTL and binary decision diagrams. The methods are very e cient and can handle all of the ISCAS'85 benchmark circuits in minutes. A c omparison of the results with traditional technology mapping using SIS on di erent libraries shows an average delay reduction above 18 for OTR, and an average delay reduction above 35 for the Static CMOS PTL method, with signi cant savings in the area. 1 Introduction Technology mapping is a cornerstone of the logic synthesis process and this area has been well studied in the past. Most existing techniques for technology mapping are based on static pre-characterized libraries, and can be classi ed into four categories: rule-based mapping 13 , graph matching 15 , direct mapping 18 and functional mapping 20. However, with changes in device technologies and the use of more complex static CMOS gates for example, in silicon-on-insulator technology, where longer transistor stacks are permitted, the limitations of the library-based design are becoming apparent. A library of xed size restricts the design choices that are available to a circuit designer, while a dynamic library that is generated on the y enables a better exploration of the This work is supported in part by a Lucent T echnologies DAC graduate scholarship, by a gift from Intel Corporation, and by the NSF under contracts MIP-9502556 and MIP-9796305. 1 design space. This paper develops techniques for generating complex gates on the y and performing technology mapping for two t ypes of technologies: Static CMOS: A topological mapping method called the odd-level transistor replacement OTR is developed for library-less mapping to complex static CMOS gates. Mixed static CMOS pass transistor logic PTL: A Boolean functional mapping method using binary decision diagrams BDD's to map logic to PTL is developed. This paper employs a similar dynamic programming based framework for both of these problems, and although they are solved as separate problems, we present them together in one publication for this reason. 1.1 Library-less mapping Traditional methods for technology mapping are directed towards a speci c library and are targeted towards objectives such as minimizing the circuit delay, minimizing the area and reducing the power dissipation. Using a pre-characterized library methodology has the inherent disadvantage that the quality of the results is dependent on the richness of the library: a library with a larger number of cells is likely to lead to better results than a sparsely populated library. The impact of the library size on logic synthesis was shown ...

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A survey for pass-transistor logic technologies-recent researches and developments and future prospects

Taki

Proceedings of 1998 Asia and South Pacific Design Automation Conference

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Synthesize pass transistor logic gate by using free binary decision diagram

Cited by 5 publications

References 6 publications

BDD‐based synthesis for mixed CMOS/PTL logic

BDD‐based synthesis for mixed CMOS/PTL logic

Technology mapping for high-performance static CMOS and pass transistor logic designs

A survey for pass-transistor logic technologies-recent researches and developments and future prospects

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